115 lines
3.5 KiB
C++
115 lines
3.5 KiB
C++
#include "system.h"
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#include "spiclass.h"
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typedef __SIZE_TYPE__ size_t;
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enum SPICLK : uint32_t {
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FPCLK_2 = 0u, // 72 MHz
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FPCLK_4, // 36 MHz
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FPCLK_8, // 18 MHz
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FPCLK_16, // 9 MHz
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FPCLK_32, // 4.5 MHz
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FPCLK_64, // 2.25 MHz
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FPCLK_128, // 1.125 MHz
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FPCLK_256, // 0.5625 MHz
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};
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static SpiClass * pSpiInstance = nullptr;
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extern "C" {
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//[[gnu::interrupt]] extern void DMA1_Channel2_IRQHandler();
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[[gnu::interrupt]] extern void DMA1_Channel3_IRQHandler();
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extern void * memcpy (void * dest, const void * src, size_t n);
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};
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void DMA1_Channel3_IRQHandler() { // transmit channel
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if (pSpiInstance) pSpiInstance->drq();
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}
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static constexpr unsigned FM = 3u; // 50 MHz
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static void InitPins () noexcept {
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// PA4 - NSS, PA5 - SCK, PA6 - MISO, PA7 - MOSI
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GPIOA.CFGLR.modify([](GPIOA_Type::CFGLR_DEF & r) -> uint32_t {
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/*r.B.MODE4 = FM;
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r.B.CNF4 = 2u; // alt push - pull
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r.B.MODE6 = 0u; // input mode
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r.B.CNF6 = 1u; // floating */
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r.B.MODE5 = FM;
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r.B.CNF5 = 2u; // alt push - pull
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r.B.MODE7 = FM;
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r.B.CNF7 = 2u; // alt push - pull
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return r.R;
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});
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// AFIO - default
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}
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void SpiClass::drq() {
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if (!driver) return;
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DMA1_Type::INTFR_DEF state (DMA1.INTFR);
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/*if (state.B.HTIF3) {
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DMA1.INTFCR.B.CHTIF3 = SET; // clear half
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} */
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if (state.B.TCIF3) {
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DMA1.INTFCR.B.CTCIF3 = SET; // clear complete
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driver->Send (ptrh, LEDS_LEN);
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}
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}
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SpiClass::SpiClass(OneWay<uint8_t> & base) noexcept : driver (& base), ptrl (buffer), ptrh (buffer + PADDING) {
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pSpiInstance = this;
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for (unsigned n=0u; n<FULL_LEN; n++) buffer[n] = 0u;
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Color * ptr = reinterpret_cast<Color*>(ptrh);
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const OneColor oz(0x00);
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for (unsigned n=0; n<NUMLEDS; n++) {
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Color & c = ptr [n];
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c.b = oz; c.g = oz; c.r = oz;
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}
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}
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void SpiClass::Init() {
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RCC.APB2PCENR.modify([](RCC_Type::APB2PCENR_DEF & r) -> uint32_t {
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r.B.SPI1EN = SET;
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r.B.IOPAEN = SET;
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r.B.AFIOEN = SET;
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return r.R;
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});
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RCC.AHBPCENR.B.DMA1EN = SET;
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InitPins();
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// Configure the peripheral data register address
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DMA1.PADDR3.R = reinterpret_cast<size_t> (& SPI1.DATAR);
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// Configure the memory address
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DMA1.MADDR3.R = reinterpret_cast<size_t> (buffer);
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// Configure the number of DMA tranfer to be performs on DMA channel 3
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DMA1.CNTR3 .R = FULL_LEN;
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// Configure increment, size, interrupts and circular mode
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DMA1.CFGR3.modify([] (DMA1_Type::CFGR3_DEF & r) -> uint32_t {
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r.B.PL = 3u; // highest priority
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r.B.DIR = SET; // memory -> periferal
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r.B.MINC = SET; // memory increment
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r.B.MSIZE = 0u; // 8-bit
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r.B.PSIZE = 0u; // 8-bit
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//r.B.HTIE = SET; // INT Enable HALF
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r.B.TCIE = SET; // INT Enable FULL
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r.B.CIRC = SET; // Circular MODE
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// Enable DMA Channel 1
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r.B.EN = SET;
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return r.R;
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});
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SPI1.CTLR1.modify([](SPI1_Type::CTLR1_DEF & r) -> uint32_t {
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r.B.CPHA = RESET;
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r.B.CPOL = RESET;
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r.B.MSTR = SET;
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r.B.DFF = RESET; // 8 bit
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r.B.SSM = SET;
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r.B.SSI = SET;
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r.B.LSBFIRST = SET;
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/* 2.25 MHz - 1bit = 444 ns
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* 1 LED => 9 x 8 x 0.444 = 32 us DMA celkem (10 + 4) x 32 = 0.448 ms
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* */
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r.B.BR = FPCLK_64;
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return r.R;
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});
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SPI1.CTLR2.modify([](SPI1_Type::CTLR2_DEF & r) -> uint32_t {
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r.B.SSOE = SET;
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//r.B.RXNEIE = SET;
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//r.B.TXEIE = SET;
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r.B.TXDMAEN = SET;
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return r.R;
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});
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NVIC.EnableIRQ(DMA1_Channel3_IRQn);
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SPI1.CTLR1.B.SPE = SET;
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}
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