90 lines
3.1 KiB
C++
90 lines
3.1 KiB
C++
#include "STM32F0x1.h"
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#include "CortexM0.h"
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#include "gpio.h"
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#include "pcmdma.h"
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typedef __SIZE_TYPE__ size_t;
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/* TIMER:
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* fs = 8000Hz, ft = 3 * fs = 24000Hz
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* reload = SystemCoreClock / ft = 48000000Hz / 24000Hz = 2000
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* PINY : +PA9[AF2], -PB0[AF2] => TIM1:CH2
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* DMA : TIM1_UP = 5
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*/
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static void Dma1Ch5Init (void * addr) {
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// Configure the peripheral data register address etc
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DMA1. CPAR5.R = reinterpret_cast<size_t> (& (TIM1.CCR2));
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DMA1. CMAR5.R = reinterpret_cast<size_t> (addr);
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DMA1.CNDTR5.R = FULL_LEN;
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// Configure increment, size, interrupts and circular mode
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DMA1.CCR5.modify([](auto & ccr) -> auto {
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ccr.B.MINC = SET;
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ccr.B.MSIZE = 1u;
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ccr.B.PSIZE = 1u;
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ccr.B.DIR = SET;
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ccr.B.HTIE = SET; // Po půlce přerušit.
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ccr.B.TCIE = SET; // Po dokončení přerušit.
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ccr.B.CIRC = SET;
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ccr.B.EN = RESET;
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return ccr.R;
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});
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}
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static PcmDma * PcmDmaInstance = nullptr;
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PcmDma::PcmDma() noexcept : pL(buffer), pH(buffer + HALF_LEN) {
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PcmDmaInstance = this;
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const GpioClass de (GpioPortA, 12);
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de << true; // použitý hardware používá jako budič sluchátek 75176 (RS485), nutno vybavit
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for (unsigned n=0; n<FULL_LEN; n++) buffer[n] = MAXPWM >> 1;
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GpioClass pin1p (GpioPortA, 9, GPIO_Mode_AF);
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GpioClass pin1n (GpioPortB, 0, GPIO_Mode_AF);
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pin1p.setAF (2);
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pin1n.setAF (2);
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// 1. Enable clock peripheral
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RCC.APB2ENR.B.TIM1EN = SET;
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RCC.AHBENR. B.DMA1EN = SET;
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// 2. Timer
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TIM1.PSC.R = 0u;
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TIM1.ARR.R = MAXPWM - 1;
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TIM1.RCR.R = 0u;
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// OC preload, CC output, Mode 6 = PWM1
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TIM1.CCMR1_Output.modify([](TIM1_Type::CCMR1_Output_DEF & r) -> auto {
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r.B.OC2PE = SET;
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r.B.OC2M = 6u;
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return r.R;
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});
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// povol pin + negaci
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TIM1.CCER.modify([](TIM1_Type::CCER_DEF & r) -> auto {
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r.B.CC2E = SET;
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r.B.CC2NE = SET;
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return r.R;
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});
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// Set Output, dead time
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TIM1.BDTR.modify([](TIM1_Type::BDTR_DEF & r) -> auto {
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//r.B.DTG = 48u; // dead: 1 us
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r.B.MOE = SET; // Main output enable
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//r.B.OSSR = 1u; // Off-state selection for Run mode - TODO
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return r.R;
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});
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// Preload
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TIM1.CR1.modify([](TIM1_Type::CR1_DEF & r) -> auto {
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r.B.ARPE = SET; // TIM1_ARR register is buffered
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r.B.URS = SET; // Only counter overflow/underflow generates an update DMA request
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return r.R;
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});
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/* Update DMA request enable
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* Spustíme DMA - sice budou dlouhé buffery, ale přerušení jen po 20ms */
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TIM1.EGR.B.UG = SET; // Reinitialize the counter and generates an update of the registers
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TIM1.DIER.B.UDE = SET; // Update DMA request enabled
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Dma1Ch5Init (buffer);
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// 3. NVIC
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NVIC_EnableIRQ (DMA1_CH4_5_6_7_DMA2_CH3_4_5_IRQn);
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TIM1.CR1.R |= 1u; // enable TIM1 (překladač bohužel bere poslední bit jako half, registr to neunese)
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DMA1.CCR5.R |= 1u; // enable DMA (dtto)
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}
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// Přerušení od DMA
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extern "C" void DMA1_CH4_5_6_7_DMA2_CH3_4_5_IRQHandler (void) {
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DMA1_Type::ISR_DEF status (DMA1.ISR);
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DMA1.IFCR.R = status.R; // clear flags
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if (!PcmDmaInstance) return;
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if (status.B.HTIF5 != RESET) PcmDmaInstance->send(false);
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else if (status.B.TCIF5 != RESET) PcmDmaInstance->send(true);
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}
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