#ifndef CH32V00xxx_HDEF
#define CH32V00xxx_HDEF
/** @brief CH32V00xxx */
/* CH32V00xxx View File */

/* IO definitions (access restrictions to peripheral registers) */
/** defines 'read only'    permissions */
#define __I volatile
/** defines 'write only'   permissions */
#define __O volatile
/** defines 'read / write' permissions */
#define __IO volatile
#include <stdint.h>
#define MERGE union
#define __MPU_PRESENT             0
#define __NVIC_PRIO_BITS          0
#define __Vendor_SysTickConfig    0
#define __FPU_PRESENT             0
enum ONE_BIT : uint32_t { RESET = 0, SET = 1 };

// ////////////////////+++ PWR +-+//////////////////// //
struct PWR_Type    { /*!< Power control */
  union CTLR_DEF   {  //!< Power control register (PWR_CTRL)
    struct {
           ONE_BIT    UNUSED0 :  1; //!<[00] 
      __IO ONE_BIT    PDDS    :  1; //!<[01] Power Down Deep Sleep
           uint32_t   UNUSED1 :  2; //!<[02] 
      __IO ONE_BIT    PVDE    :  1; //!<[04] Power Voltage Detector Enable
      __IO uint32_t   PLS     :  3; //!<[05] PVD Level Selection
    } B;
    __IO uint32_t  R;
    explicit CTLR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CTLR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CTLR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CSR_DEF    {  //!< Power control state register (PWR_CSR)
    struct {
           uint32_t   UNUSED0 :  2; //!<[00] 
      __I  ONE_BIT    PVDO    :  1; //!<[02] PVD Output
    } B;
    __IO uint32_t  R;
    explicit CSR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CSR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CSR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union AWUCSR_DEF {  //!< Automatic wake-up control state register (PWR_AWUCSR)
    struct {
           ONE_BIT  UNUSED0 :  1; //!<[00] 
      __IO ONE_BIT  AWUEN   :  1; //!<[01] Automatic wake-up enable
    } B;
    __IO uint32_t  R;
    explicit AWUCSR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      AWUCSR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      AWUCSR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union AWUAPR_DEF {  //!< Automatic wake window comparison value register (PWR_AWUAPR)
    struct {
      __IO uint32_t   AWUAPR :  6; //!<[00] AWU window value
    } B;
    __IO uint32_t  R;
    explicit AWUAPR_DEF () noexcept { R = 0x0000003fu; }
    template<typename F> void setbit (F f) volatile {
      AWUAPR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      AWUAPR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union AWUPSC_DEF {  //!< Automatic wake-up prescaler register (PWR_AWUPSC)
    struct {
      __IO uint32_t   AWUPSC :  4; //!<[00] Wake-up prescaler
    } B;
    __IO uint32_t  R;
    explicit AWUPSC_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      AWUPSC_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      AWUPSC_DEF r; r.R = R;
      R = f (r);
    }
  };
  // PERIPHERAL PWR REGISTERS INSTANCES
  __IO CTLR_DEF              CTLR ;  //!< [0000](04)[0x00000000]
  __IO CSR_DEF                CSR ;  //!< [0004](04)[0x00000000]
  __IO AWUCSR_DEF          AWUCSR ;  //!< [0008](04)[0x00000000]
  __IO AWUAPR_DEF          AWUAPR ;  //!< [000c](04)[0x0000003F]
  __IO AWUPSC_DEF          AWUPSC ;  //!< [0010](04)[0x00000000]
}; /* total size = 0x0400, struct size = 0x0014 */

// ////////////////////+++ RCC +-+//////////////////// //
struct RCC_Type    { /*!< Reset and clock control */
  union CTLR_DEF      {  //!< Clock control register
    struct {
      __IO ONE_BIT    HSION   :  1; //!<[00] Internal High Speed clock enable
      __I  ONE_BIT    HSIRDY  :  1; //!<[01] Internal High Speed clock ready flag
           ONE_BIT    UNUSED0 :  1; //!<[02] 
      __IO uint32_t   HSITRIM :  5; //!<[03] Internal High Speed clock trimming
      __I  uint32_t   HSICAL  :  8; //!<[08] Internal High Speed clock Calibration
      __IO ONE_BIT    HSEON   :  1; //!<[16] External High Speed clock enable
      __I  ONE_BIT    HSERDY  :  1; //!<[17] External High Speed clock ready flag
      __IO ONE_BIT    HSEBYP  :  1; //!<[18] External High Speed clock Bypass
      __IO ONE_BIT    CSSON   :  1; //!<[19] Clock Security System enable
           uint32_t   UNUSED1 :  4; //!<[20] 
      __IO ONE_BIT    PLLON   :  1; //!<[24] PLL enable
      __I  ONE_BIT    PLLRDY  :  1; //!<[25] PLL clock ready flag
    } B;
    __IO uint32_t  R;
    explicit CTLR_DEF () noexcept { R = 0x00000083u; }
    template<typename F> void setbit (F f) volatile {
      CTLR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CTLR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CFGR0_DEF     {  //!< Clock configuration register (RCC_CFGR0)
    struct {
      __IO uint32_t   SW      :  2; //!<[00] System clock Switch
      __I  uint32_t   SWS     :  2; //!<[02] System Clock Switch Status
      __IO uint32_t   HPRE    :  4; //!<[04] AHB prescaler
      __IO uint32_t   PPRE1   :  3; //!<[08] APB Low speed prescaler (APB1)
      __IO uint32_t   PPRE2   :  3; //!<[11] APB High speed prescaler (APB2)
      __IO uint32_t   ADCPRE  :  2; //!<[14] ADC prescaler
      __IO ONE_BIT    PLLSRC  :  1; //!<[16] PLL entry clock source
           uint32_t   UNUSED0 :  7; //!<[17] 
      __IO uint32_t   MCO     :  3; //!<[24] Microcontroller clock output
    } B;
    __IO uint32_t  R;
    explicit CFGR0_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CFGR0_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CFGR0_DEF r; r.R = R;
      R = f (r);
    }
  };
  union INTR_DEF      {  //!< Clock interrupt register (RCC_INTR)
    struct {
      __I  ONE_BIT    LSIRDYF  :  1; //!<[00] LSI Ready Interrupt flag
           ONE_BIT    UNUSED0  :  1; //!<[01] 
      __I  ONE_BIT    HSIRDYF  :  1; //!<[02] HSI Ready Interrupt flag
      __I  ONE_BIT    HSERDYF  :  1; //!<[03] HSE Ready Interrupt flag
      __I  ONE_BIT    PLLRDYF  :  1; //!<[04] PLL Ready Interrupt flag
           uint32_t   UNUSED1  :  2; //!<[05] 
      __I  ONE_BIT    CSSF     :  1; //!<[07] Clock Security System Interrupt flag
      __IO ONE_BIT    LSIRDYIE :  1; //!<[08] LSI Ready Interrupt Enable
           ONE_BIT    UNUSED2  :  1; //!<[09] 
      __IO ONE_BIT    HSIRDYIE :  1; //!<[10] HSI Ready Interrupt Enable
      __IO ONE_BIT    HSERDYIE :  1; //!<[11] HSE Ready Interrupt Enable
      __IO ONE_BIT    PLLRDYIE :  1; //!<[12] PLL Ready Interrupt Enable
           uint32_t   UNUSED3  :  3; //!<[13] 
      __O  ONE_BIT    LSIRDYC  :  1; //!<[16] LSI Ready Interrupt Clear
           ONE_BIT    UNUSED4  :  1; //!<[17] 
      __O  ONE_BIT    HSIRDYC  :  1; //!<[18] HSI Ready Interrupt Clear
      __O  ONE_BIT    HSERDYC  :  1; //!<[19] HSE Ready Interrupt Clear
      __O  ONE_BIT    PLLRDYC  :  1; //!<[20] PLL Ready Interrupt Clear
           uint32_t   UNUSED5  :  2; //!<[21] 
      __O  ONE_BIT    CSSC     :  1; //!<[23] Clock security system interrupt clear
    } B;
    __IO uint32_t  R;
    explicit INTR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      INTR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      INTR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union APB2PRSTR_DEF {  //!< APB2 peripheral reset register (RCC_APB2PRSTR)
    struct {
      __IO ONE_BIT    AFIORST   :  1; //!<[00] Alternate function I/O reset
           ONE_BIT    UNUSED0   :  1; //!<[01] 
      __IO ONE_BIT    IOPARST   :  1; //!<[02] IO port A reset
           ONE_BIT    UNUSED1   :  1; //!<[03] 
      __IO ONE_BIT    IOPCRST   :  1; //!<[04] IO port C reset
      __IO ONE_BIT    IOPDRST   :  1; //!<[05] IO port D reset
           uint32_t   UNUSED2   :  3; //!<[06] 
      __IO ONE_BIT    ADC1RST   :  1; //!<[09] ADC 1 interface reset
           ONE_BIT    UNUSED3   :  1; //!<[10] 
      __IO ONE_BIT    TIM1RST   :  1; //!<[11] TIM1 timer reset
      __IO ONE_BIT    SPI1RST   :  1; //!<[12] SPI 1 reset
           ONE_BIT    UNUSED4   :  1; //!<[13] 
      __IO ONE_BIT    USART1RST :  1; //!<[14] USART1 reset
    } B;
    __IO uint32_t  R;
    explicit APB2PRSTR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      APB2PRSTR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      APB2PRSTR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union APB1PRSTR_DEF {  //!< APB1 peripheral reset register (RCC_APB1PRSTR)
    struct {
           uint32_t   UNUSED0 : 11; //!<[00] 
      __IO ONE_BIT    WWDGRST :  1; //!<[11] Window watchdog reset
           uint32_t   UNUSED1 :  9; //!<[12] 
      __IO ONE_BIT    I2C1RST :  1; //!<[21] I2C1 reset
           uint32_t   UNUSED2 :  6; //!<[22] 
      __IO ONE_BIT    PWRRST  :  1; //!<[28] Power interface reset
    } B;
    __IO uint32_t  R;
    explicit APB1PRSTR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      APB1PRSTR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      APB1PRSTR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union AHBPCENR_DEF  {  //!< AHB Peripheral Clock enable register (RCC_AHBPCENR)
    struct {
      __IO ONE_BIT  DMA1EN  :  1; //!<[00] DMA clock enable
           ONE_BIT  UNUSED0 :  1; //!<[01] 
      __IO ONE_BIT  SRAMEN  :  1; //!<[02] SRAM interface clock enable
    } B;
    __IO uint32_t  R;
    explicit AHBPCENR_DEF () noexcept { R = 0x00000004u; }
    template<typename F> void setbit (F f) volatile {
      AHBPCENR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      AHBPCENR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union APB2PCENR_DEF {  //!< APB2 peripheral clock enable register (RCC_APB2PCENR)
    struct {
      __IO ONE_BIT    AFIOEN   :  1; //!<[00] Alternate function I/O clock enable
           ONE_BIT    UNUSED0  :  1; //!<[01] 
      __IO ONE_BIT    IOPAEN   :  1; //!<[02] I/O port A clock enable
           ONE_BIT    UNUSED1  :  1; //!<[03] 
      __IO ONE_BIT    IOPCEN   :  1; //!<[04] I/O port C clock enable
      __IO ONE_BIT    IOPDEN   :  1; //!<[05] I/O port D clock enable
           uint32_t   UNUSED2  :  3; //!<[06] 
      __IO ONE_BIT    ADC1EN   :  1; //!<[09] ADC1 interface clock enable
           ONE_BIT    UNUSED3  :  1; //!<[10] 
      __IO ONE_BIT    TIM1EN   :  1; //!<[11] TIM1 Timer clock enable
      __IO ONE_BIT    SPI1EN   :  1; //!<[12] SPI 1 clock enable
           ONE_BIT    UNUSED4  :  1; //!<[13] 
      __IO ONE_BIT    USART1EN :  1; //!<[14] USART1 clock enable
    } B;
    __IO uint32_t  R;
    explicit APB2PCENR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      APB2PCENR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      APB2PCENR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union APB1PCENR_DEF {  //!< APB1 peripheral clock enable register (RCC_APB1PCENR)
    struct {
      __IO ONE_BIT    TIM2EN  :  1; //!<[00] Timer 2 clock enable
           uint32_t   UNUSED0 : 10; //!<[01] 
      __IO ONE_BIT    WWDGEN  :  1; //!<[11] Window watchdog clock enable
           uint32_t   UNUSED1 :  9; //!<[12] 
      __IO ONE_BIT    I2C1EN  :  1; //!<[21] I2C 1 clock enable
           uint32_t   UNUSED2 :  6; //!<[22] 
      __IO ONE_BIT    PWREN   :  1; //!<[28] Power interface clock enable
    } B;
    __IO uint32_t  R;
    explicit APB1PCENR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      APB1PCENR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      APB1PCENR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union RSTSCKR_DEF   {  //!< Control/status register (RCC_RSTSCKR)
    struct {
      __IO ONE_BIT    LSION    :  1; //!<[00] Internal low speed oscillator enable
      __I  ONE_BIT    LSIRDY   :  1; //!<[01] Internal low speed oscillator ready
           uint32_t   UNUSED0  : 22; //!<[02] 
      __IO ONE_BIT    RMVF     :  1; //!<[24] Remove reset flag
           ONE_BIT    UNUSED1  :  1; //!<[25] 
      __I  ONE_BIT    PINRSTF  :  1; //!<[26] PIN reset flag
      __I  ONE_BIT    PORRSTF  :  1; //!<[27] POR/PDR reset flag
      __I  ONE_BIT    SFTRSTF  :  1; //!<[28] Software reset flag
      __I  ONE_BIT    IWDGRSTF :  1; //!<[29] Independent watchdog reset flag
      __I  ONE_BIT    WWDGRSTF :  1; //!<[30] Window watchdog reset flag
      __I  ONE_BIT    LPWRRSTF :  1; //!<[31] Low-power reset flag
    } B;
    __IO uint32_t  R;
    explicit RSTSCKR_DEF () noexcept { R = 0x0c000000u; }
    template<typename F> void setbit (F f) volatile {
      RSTSCKR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      RSTSCKR_DEF r; r.R = R;
      R = f (r);
    }
  };
  // PERIPHERAL RCC REGISTERS INSTANCES
  __IO CTLR_DEF                 CTLR ;  //!< [0000](04)[0x00000083]
  __IO CFGR0_DEF               CFGR0 ;  //!< [0004](04)[0x00000000]
  __IO INTR_DEF                 INTR ;  //!< [0008](04)[0x00000000]
  __IO APB2PRSTR_DEF       APB2PRSTR ;  //!< [000c](04)[0x00000000]
  __IO APB1PRSTR_DEF       APB1PRSTR ;  //!< [0010](04)[0x00000000]
  __IO AHBPCENR_DEF         AHBPCENR ;  //!< [0014](04)[0x00000004]
  __IO APB2PCENR_DEF       APB2PCENR ;  //!< [0018](04)[0x00000000]
  __IO APB1PCENR_DEF       APB1PCENR ;  //!< [001c](04)[0x00000000]
       uint32_t            UNUSED0 ;  //!< [0020](04)[0xFFFFFFFF]
  __IO RSTSCKR_DEF           RSTSCKR ;  //!< [0024](04)[0x0C000000]
}; /* total size = 0x0400, struct size = 0x0028 */

// ////////////////////+++ EXTEND +-+//////////////////// //
struct EXTEND_Type { /*!<  Extend configuration */
  union EXTEND_CTR_DEF {  //!< Configure the extended control register
    struct {
      __IO uint32_t   PLL_CFG        :  4; //!<[00] Configure the PLL clock delay time
           uint32_t   UNUSED0        :  2; //!<[04] 
      __IO ONE_BIT    LOCKUP_EN      :  1; //!<[06] LOCKUP_Enable
      __IO ONE_BIT    LOCKUP_RESET   :  1; //!<[07] LOCKUP RESET
           uint32_t   UNUSED1        :  2; //!<[08] 
      __IO ONE_BIT    LDO_TRIM       :  1; //!<[10] LDO_TRIM
      __IO uint32_t   FLASH_CLK_TRIM :  3; //!<[11] FLASH clock trimming
      __IO ONE_BIT    WR_EN          :  1; //!<[14] Control Register write enable
      __IO ONE_BIT    WR_LOCK        :  1; //!<[15] Control Register write lock
      __IO ONE_BIT    OPA_EN         :  1; //!<[16] OPA Enalbe
      __IO ONE_BIT    OPA_NSEL       :  1; //!<[17] OPA negative end channel selection
      __IO ONE_BIT    OPA_PSEL       :  1; //!<[18] OPA positive end channel selection
    } B;
    __IO uint32_t  R;
    explicit EXTEND_CTR_DEF () noexcept { R = 0x00000040u; }
    template<typename F> void setbit (F f) volatile {
      EXTEND_CTR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      EXTEND_CTR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union EXTEND_KR_DEF  {  //!< Configure the extended key register
    struct {
      __O  uint32_t   KEY : 32; //!<[00] Write key value
    } B;
    __IO uint32_t  R;
    explicit EXTEND_KR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      EXTEND_KR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      EXTEND_KR_DEF r; r.R = R;
      R = f (r);
    }
  };
  // PERIPHERAL EXTEND REGISTERS INSTANCES
  __IO EXTEND_CTR_DEF      EXTEND_CTR ;  //!< [0000](04)[0x00000040]
  __IO EXTEND_KR_DEF        EXTEND_KR ;  //!< [0004](04)[0x00000000]
}; /* total size = 0x0400, struct size = 0x0008 */

// ////////////////////+++ GPIOA +-+//////////////////// //
struct GPIOA_Type  { /*!< General purpose I/O */
  union CFGLR_DEF   {  //!< Port configuration register low (GPIOn_CFGLR)
    struct {
      __IO uint32_t   MODE0 :  2; //!<[00] Port n.0 mode bits
      __IO uint32_t   CNF0  :  2; //!<[02] Port n.0 configuration bits
      __IO uint32_t   MODE1 :  2; //!<[04] Port n.1 mode bits
      __IO uint32_t   CNF1  :  2; //!<[06] Port n.1 configuration bits
      __IO uint32_t   MODE2 :  2; //!<[08] Port n.2 mode bits
      __IO uint32_t   CNF2  :  2; //!<[10] Port n.2 configuration bits
      __IO uint32_t   MODE3 :  2; //!<[12] Port n.3 mode bits
      __IO uint32_t   CNF3  :  2; //!<[14] Port n.3 configuration bits
      __IO uint32_t   MODE4 :  2; //!<[16] Port n.4 mode bits
      __IO uint32_t   CNF4  :  2; //!<[18] Port n.4 configuration bits
      __IO uint32_t   MODE5 :  2; //!<[20] Port n.5 mode bits
      __IO uint32_t   CNF5  :  2; //!<[22] Port n.5 configuration bits
      __IO uint32_t   MODE6 :  2; //!<[24] Port n.6 mode bits
      __IO uint32_t   CNF6  :  2; //!<[26] Port n.6 configuration bits
      __IO uint32_t   MODE7 :  2; //!<[28] Port n.7 mode bits
      __IO uint32_t   CNF7  :  2; //!<[30] Port n.7 configuration bits
    } B;
    __IO uint32_t  R;
    explicit CFGLR_DEF () noexcept { R = 0x44444444u; }
    template<typename F> void setbit (F f) volatile {
      CFGLR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CFGLR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union INDR_DEF    {  //!< Port input data register (GPIOn_INDR)
    struct {
      __I  ONE_BIT  IDR0 :  1; //!<[00] Port input data
      __I  ONE_BIT  IDR1 :  1; //!<[01] Port input data
      __I  ONE_BIT  IDR2 :  1; //!<[02] Port input data
      __I  ONE_BIT  IDR3 :  1; //!<[03] Port input data
      __I  ONE_BIT  IDR4 :  1; //!<[04] Port input data
      __I  ONE_BIT  IDR5 :  1; //!<[05] Port input data
      __I  ONE_BIT  IDR6 :  1; //!<[06] Port input data
      __I  ONE_BIT  IDR7 :  1; //!<[07] Port input data
    } B;
    __I  uint32_t  R;

    explicit INDR_DEF (volatile INDR_DEF & o) noexcept { R = o.R; };
  };
  union OUTDR_DEF   {  //!< Port output data register (GPIOn_OUTDR)
    struct {
      __IO ONE_BIT  ODR0 :  1; //!<[00] Port output data
      __IO ONE_BIT  ODR1 :  1; //!<[01] Port output data
      __IO ONE_BIT  ODR2 :  1; //!<[02] Port output data
      __IO ONE_BIT  ODR3 :  1; //!<[03] Port output data
      __IO ONE_BIT  ODR4 :  1; //!<[04] Port output data
      __IO ONE_BIT  ODR5 :  1; //!<[05] Port output data
      __IO ONE_BIT  ODR6 :  1; //!<[06] Port output data
      __IO ONE_BIT  ODR7 :  1; //!<[07] Port output data
    } B;
    __IO uint32_t  R;
    explicit OUTDR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      OUTDR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      OUTDR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union BSHR_DEF    {  //!< Port bit set/reset register (GPIOn_BSHR)
    struct {
      __O  ONE_BIT    BS0     :  1; //!<[00] Set bit 0
      __O  ONE_BIT    BS1     :  1; //!<[01] Set bit 1
      __O  ONE_BIT    BS2     :  1; //!<[02] Set bit 1
      __O  ONE_BIT    BS3     :  1; //!<[03] Set bit 3
      __O  ONE_BIT    BS4     :  1; //!<[04] Set bit 4
      __O  ONE_BIT    BS5     :  1; //!<[05] Set bit 5
      __O  ONE_BIT    BS6     :  1; //!<[06] Set bit 6
      __O  ONE_BIT    BS7     :  1; //!<[07] Set bit 7
           uint32_t   UNUSED0 :  8; //!<[08] 
      __O  ONE_BIT    BR0     :  1; //!<[16] Reset bit 0
      __O  ONE_BIT    BR1     :  1; //!<[17] Reset bit 1
      __O  ONE_BIT    BR2     :  1; //!<[18] Reset bit 2
      __O  ONE_BIT    BR3     :  1; //!<[19] Reset bit 3
      __O  ONE_BIT    BR4     :  1; //!<[20] Reset bit 4
      __O  ONE_BIT    BR5     :  1; //!<[21] Reset bit 5
      __O  ONE_BIT    BR6     :  1; //!<[22] Reset bit 6
      __O  ONE_BIT    BR7     :  1; //!<[23] Reset bit 7
    } B;
    __O  uint32_t  R;
    explicit BSHR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      BSHR_DEF r;
      R = f (r);
    }
  };
  union BCR_DEF     {  //!< Port bit reset register (GPIOn_BCR)
    struct {
      __O  ONE_BIT  BR0 :  1; //!<[00] Reset bit 0
      __O  ONE_BIT  BR1 :  1; //!<[01] Reset bit 1
      __O  ONE_BIT  BR2 :  1; //!<[02] Reset bit 1
      __O  ONE_BIT  BR3 :  1; //!<[03] Reset bit 3
      __O  ONE_BIT  BR4 :  1; //!<[04] Reset bit 4
      __O  ONE_BIT  BR5 :  1; //!<[05] Reset bit 5
      __O  ONE_BIT  BR6 :  1; //!<[06] Reset bit 6
      __O  ONE_BIT  BR7 :  1; //!<[07] Reset bit 7
    } B;
    __O  uint32_t  R;
    explicit BCR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      BCR_DEF r;
      R = f (r);
    }
  };
  union LCKR_DEF    {  //!< Port configuration lock register
    struct {
      __IO ONE_BIT  LCK0 :  1; //!<[00] Port A Lock bit 0
      __IO ONE_BIT  LCK1 :  1; //!<[01] Port A Lock bit 1
      __IO ONE_BIT  LCK2 :  1; //!<[02] Port A Lock bit 2
      __IO ONE_BIT  LCK3 :  1; //!<[03] Port A Lock bit 3
      __IO ONE_BIT  LCK4 :  1; //!<[04] Port A Lock bit 4
      __IO ONE_BIT  LCK5 :  1; //!<[05] Port A Lock bit 5
      __IO ONE_BIT  LCK6 :  1; //!<[06] Port A Lock bit 6
      __IO ONE_BIT  LCK7 :  1; //!<[07] Port A Lock bit 7
      __IO ONE_BIT  LCKK :  1; //!<[08] Lock key
    } B;
    __IO uint32_t  R;
    explicit LCKR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      LCKR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      LCKR_DEF r; r.R = R;
      R = f (r);
    }
  };
  // PERIPHERAL GPIOA REGISTERS INSTANCES
  __IO CFGLR_DEF             CFGLR ;  //!< [0000](04)[0x44444444]
       uint32_t          UNUSED0 ;  //!< [0004](04)[0xFFFFFFFF]
  __I  INDR_DEF               INDR ;  //!< [0008](04)[0x00000000]
  __IO OUTDR_DEF             OUTDR ;  //!< [000c](04)[0x00000000]
  __O  BSHR_DEF               BSHR ;  //!< [0010](04)[0x00000000]
  __O  BCR_DEF                 BCR ;  //!< [0014](04)[0x00000000]
  __IO LCKR_DEF               LCKR ;  //!< [0018](04)[0x00000000]
}; /* total size = 0x0400, struct size = 0x001C */

// ////////////////////+++ AFIO +-+//////////////////// //
struct AFIO_Type   { /*!< Alternate function I/O */
  union PCFR_DEF    {  //!< AF remap and debug I/O configuration register (AFIO_PCFR)
    struct {
      __IO ONE_BIT    SPI1RM          :  1; //!<[00] SPI1 remapping
      __IO ONE_BIT    I2C1RM          :  1; //!<[01] I2C1 remapping
      __IO ONE_BIT    USART1RM        :  1; //!<[02] USART1 remapping
           uint32_t   UNUSED0         :  3; //!<[03] 
      __IO uint32_t   TIM1RM          :  2; //!<[06] TIM1 remapping
      __IO uint32_t   TIM2RM          :  2; //!<[08] TIM2 remapping
           uint32_t   UNUSED1         :  5; //!<[10] 
      __IO ONE_BIT    PA12RM          :  1; //!<[15] Port A1/Port A2 mapping on OSCIN/OSCOUT
           ONE_BIT    UNUSED2         :  1; //!<[16] 
      __IO ONE_BIT    ADC1_ETRGINJ_RM :  1; //!<[17] ADC 1 External trigger injected conversion remapping
      __IO ONE_BIT    ADC1_ETRGREG_RM :  1; //!<[18] ADC 1 external trigger regular conversion remapping
           uint32_t   UNUSED3         :  2; //!<[19] 
      __IO ONE_BIT    USART1REMAP1    :  1; //!<[21] USART1 remapping
      __IO ONE_BIT    I2C1REMAP1      :  1; //!<[22] I2C1 remapping
      __IO ONE_BIT    TIM1_IREMAP     :  1; //!<[23] TIM1_CH1 channel selection
      __O  uint32_t   SWCFG           :  3; //!<[24] Serial wire JTAG configuration
    } B;
    __IO uint32_t  R;
    explicit PCFR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      PCFR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      PCFR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union EXTICR_DEF  {  //!< External interrupt configuration register (AFIO_EXTICR)
    struct {
      __IO uint32_t   EXTI0 :  2; //!<[00] EXTI0 configuration
      __IO uint32_t   EXTI1 :  2; //!<[02] EXTI1 configuration
      __IO uint32_t   EXTI2 :  2; //!<[04] EXTI2 configuration
      __IO uint32_t   EXTI3 :  2; //!<[06] EXTI3 configuration
      __IO uint32_t   EXTI4 :  2; //!<[08] EXTI4 configuration
      __IO uint32_t   EXTI5 :  2; //!<[10] EXTI5 configuration
      __IO uint32_t   EXTI6 :  2; //!<[12] EXTI6 configuration
      __IO uint32_t   EXTI7 :  2; //!<[14] EXTI7 configuration
    } B;
    __IO uint32_t  R;
    explicit EXTICR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      EXTICR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      EXTICR_DEF r; r.R = R;
      R = f (r);
    }
  };
  // PERIPHERAL AFIO REGISTERS INSTANCES
       uint32_t          UNUSED0 ;  //!< [0000](04)[0xFFFFFFFF]
  __IO PCFR_DEF               PCFR ;  //!< [0004](04)[0x00000000]
  __IO EXTICR_DEF           EXTICR ;  //!< [0008](04)[0x00000000]
}; /* total size = 0x0400, struct size = 0x000C */

// ////////////////////+++ EXTI +-+//////////////////// //
struct EXTI_Type   { /*!< EXTI */
  union INTENR_DEF {  //!< Interrupt mask register (EXTI_INTENR)
    struct {
      __IO ONE_BIT  MR0 :  1; //!<[00] Interrupt Mask on line 0
      __IO ONE_BIT  MR1 :  1; //!<[01] Interrupt Mask on line 1
      __IO ONE_BIT  MR2 :  1; //!<[02] Interrupt Mask on line 2
      __IO ONE_BIT  MR3 :  1; //!<[03] Interrupt Mask on line 3
      __IO ONE_BIT  MR4 :  1; //!<[04] Interrupt Mask on line 4
      __IO ONE_BIT  MR5 :  1; //!<[05] Interrupt Mask on line 5
      __IO ONE_BIT  MR6 :  1; //!<[06] Interrupt Mask on line 6
      __IO ONE_BIT  MR7 :  1; //!<[07] Interrupt Mask on line 7
      __IO ONE_BIT  MR8 :  1; //!<[08] Interrupt Mask on line 8
      __IO ONE_BIT  MR9 :  1; //!<[09] Interrupt Mask on line 9
    } B;
    __IO uint32_t  R;
    explicit INTENR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      INTENR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      INTENR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union EVENR_DEF  {  //!< Event mask register (EXTI_EVENR)
    struct {
      __IO ONE_BIT  MR0 :  1; //!<[00] Event Mask on line 0
      __IO ONE_BIT  MR1 :  1; //!<[01] Event Mask on line 1
      __IO ONE_BIT  MR2 :  1; //!<[02] Event Mask on line 2
      __IO ONE_BIT  MR3 :  1; //!<[03] Event Mask on line 3
      __IO ONE_BIT  MR4 :  1; //!<[04] Event Mask on line 4
      __IO ONE_BIT  MR5 :  1; //!<[05] Event Mask on line 5
      __IO ONE_BIT  MR6 :  1; //!<[06] Event Mask on line 6
      __IO ONE_BIT  MR7 :  1; //!<[07] Event Mask on line 7
      __IO ONE_BIT  MR8 :  1; //!<[08] Event Mask on line 8
      __IO ONE_BIT  MR9 :  1; //!<[09] Event Mask on line 9
    } B;
    __IO uint32_t  R;
    explicit EVENR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      EVENR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      EVENR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union RTENR_DEF  {  //!< Rising Trigger selection register (EXTI_RTENR)
    struct {
      __IO ONE_BIT  TR0 :  1; //!<[00] Rising trigger event configuration of line 0
      __IO ONE_BIT  TR1 :  1; //!<[01] Rising trigger event configuration of line 1
      __IO ONE_BIT  TR2 :  1; //!<[02] Rising trigger event configuration of line 2
      __IO ONE_BIT  TR3 :  1; //!<[03] Rising trigger event configuration of line 3
      __IO ONE_BIT  TR4 :  1; //!<[04] Rising trigger event configuration of line 4
      __IO ONE_BIT  TR5 :  1; //!<[05] Rising trigger event configuration of line 5
      __IO ONE_BIT  TR6 :  1; //!<[06] Rising trigger event configuration of line 6
      __IO ONE_BIT  TR7 :  1; //!<[07] Rising trigger event configuration of line 7
      __IO ONE_BIT  TR8 :  1; //!<[08] Rising trigger event configuration of line 8
      __IO ONE_BIT  TR9 :  1; //!<[09] Rising trigger event configuration of line 9
    } B;
    __IO uint32_t  R;
    explicit RTENR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      RTENR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      RTENR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union FTENR_DEF  {  //!< Falling Trigger selection register (EXTI_FTENR)
    struct {
      __IO ONE_BIT  TR0 :  1; //!<[00] Falling trigger event configuration of line 0
      __IO ONE_BIT  TR1 :  1; //!<[01] Falling trigger event configuration of line 1
      __IO ONE_BIT  TR2 :  1; //!<[02] Falling trigger event configuration of line 2
      __IO ONE_BIT  TR3 :  1; //!<[03] Falling trigger event configuration of line 3
      __IO ONE_BIT  TR4 :  1; //!<[04] Falling trigger event configuration of line 4
      __IO ONE_BIT  TR5 :  1; //!<[05] Falling trigger event configuration of line 5
      __IO ONE_BIT  TR6 :  1; //!<[06] Falling trigger event configuration of line 6
      __IO ONE_BIT  TR7 :  1; //!<[07] Falling trigger event configuration of line 7
      __IO ONE_BIT  TR8 :  1; //!<[08] Falling trigger event configuration of line 8
      __IO ONE_BIT  TR9 :  1; //!<[09] Falling trigger event configuration of line 9
    } B;
    __IO uint32_t  R;
    explicit FTENR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      FTENR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      FTENR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union SWIEVR_DEF {  //!< Software interrupt event register (EXTI_SWIEVR)
    struct {
      __IO ONE_BIT  SWIER0 :  1; //!<[00] Software Interrupt on line 0
      __IO ONE_BIT  SWIER1 :  1; //!<[01] Software Interrupt on line 1
      __IO ONE_BIT  SWIER2 :  1; //!<[02] Software Interrupt on line 2
      __IO ONE_BIT  SWIER3 :  1; //!<[03] Software Interrupt on line 3
      __IO ONE_BIT  SWIER4 :  1; //!<[04] Software Interrupt on line 4
      __IO ONE_BIT  SWIER5 :  1; //!<[05] Software Interrupt on line 5
      __IO ONE_BIT  SWIER6 :  1; //!<[06] Software Interrupt on line 6
      __IO ONE_BIT  SWIER7 :  1; //!<[07] Software Interrupt on line 7
      __IO ONE_BIT  SWIER8 :  1; //!<[08] Software Interrupt on line 8
      __IO ONE_BIT  SWIER9 :  1; //!<[09] Software Interrupt on line 9
    } B;
    __IO uint32_t  R;
    explicit SWIEVR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      SWIEVR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      SWIEVR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union INTFR_DEF  {  //!< Pending register (EXTI_INTFR)
    struct {
      __IO ONE_BIT  PR0 :  1; //!<[00] Pending bit 0
      __IO ONE_BIT  PR1 :  1; //!<[01] Pending bit 1
      __IO ONE_BIT  PR2 :  1; //!<[02] Pending bit 2
      __IO ONE_BIT  PR3 :  1; //!<[03] Pending bit 3
      __IO ONE_BIT  PR4 :  1; //!<[04] Pending bit 4
      __IO ONE_BIT  PR5 :  1; //!<[05] Pending bit 5
      __IO ONE_BIT  PR6 :  1; //!<[06] Pending bit 6
      __IO ONE_BIT  PR7 :  1; //!<[07] Pending bit 7
      __IO ONE_BIT  PR8 :  1; //!<[08] Pending bit 8
      __IO ONE_BIT  PR9 :  1; //!<[09] Pending bit 9
    } B;
    __IO uint32_t  R;
    explicit INTFR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      INTFR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      INTFR_DEF r; r.R = R;
      R = f (r);
    }
  };
  // PERIPHERAL EXTI REGISTERS INSTANCES
  __IO INTENR_DEF          INTENR ;  //!< [0000](04)[0x00000000]
  __IO EVENR_DEF            EVENR ;  //!< [0004](04)[0x00000000]
  __IO RTENR_DEF            RTENR ;  //!< [0008](04)[0x00000000]
  __IO FTENR_DEF            FTENR ;  //!< [000c](04)[0x00000000]
  __IO SWIEVR_DEF          SWIEVR ;  //!< [0010](04)[0x00000000]
  __IO INTFR_DEF            INTFR ;  //!< [0014](04)[0x00000000]
}; /* total size = 0x0400, struct size = 0x0018 */

// ////////////////////+++ DMA1 +-+//////////////////// //
struct DMA1_Type   { /*!< DMA1 controller */
  union INTFR_DEF   {  //!< DMA interrupt status register (DMA_INTFR)
    struct {
      __I  ONE_BIT  GIF1  :  1; //!<[00] Channel 1 Global interrupt flag
      __I  ONE_BIT  TCIF1 :  1; //!<[01] Channel 1 Transfer Complete flag
      __I  ONE_BIT  HTIF1 :  1; //!<[02] Channel 1 Half Transfer Complete flag
      __I  ONE_BIT  TEIF1 :  1; //!<[03] Channel 1 Transfer Error flag
      __I  ONE_BIT  GIF2  :  1; //!<[04] Channel 2 Global interrupt flag
      __I  ONE_BIT  TCIF2 :  1; //!<[05] Channel 2 Transfer Complete flag
      __I  ONE_BIT  HTIF2 :  1; //!<[06] Channel 2 Half Transfer Complete flag
      __I  ONE_BIT  TEIF2 :  1; //!<[07] Channel 2 Transfer Error flag
      __I  ONE_BIT  GIF3  :  1; //!<[08] Channel 3 Global interrupt flag
      __I  ONE_BIT  TCIF3 :  1; //!<[09] Channel 3 Transfer Complete flag
      __I  ONE_BIT  HTIF3 :  1; //!<[10] Channel 3 Half Transfer Complete flag
      __I  ONE_BIT  TEIF3 :  1; //!<[11] Channel 3 Transfer Error flag
      __I  ONE_BIT  GIF4  :  1; //!<[12] Channel 4 Global interrupt flag
      __I  ONE_BIT  TCIF4 :  1; //!<[13] Channel 4 Transfer Complete flag
      __I  ONE_BIT  HTIF4 :  1; //!<[14] Channel 4 Half Transfer Complete flag
      __I  ONE_BIT  TEIF4 :  1; //!<[15] Channel 4 Transfer Error flag
      __I  ONE_BIT  GIF5  :  1; //!<[16] Channel 5 Global interrupt flag
      __I  ONE_BIT  TCIF5 :  1; //!<[17] Channel 5 Transfer Complete flag
      __I  ONE_BIT  HTIF5 :  1; //!<[18] Channel 5 Half Transfer Complete flag
      __I  ONE_BIT  TEIF5 :  1; //!<[19] Channel 5 Transfer Error flag
      __I  ONE_BIT  GIF6  :  1; //!<[20] Channel 6 Global interrupt flag
      __I  ONE_BIT  TCIF6 :  1; //!<[21] Channel 6 Transfer Complete flag
      __I  ONE_BIT  HTIF6 :  1; //!<[22] Channel 6 Half Transfer Complete flag
      __I  ONE_BIT  TEIF6 :  1; //!<[23] Channel 6 Transfer Error flag
      __I  ONE_BIT  GIF7  :  1; //!<[24] Channel 7 Global interrupt flag
      __I  ONE_BIT  TCIF7 :  1; //!<[25] Channel 7 Transfer Complete flag
      __I  ONE_BIT  HTIF7 :  1; //!<[26] Channel 7 Half Transfer Complete flag
      __I  ONE_BIT  TEIF7 :  1; //!<[27] Channel 7 Transfer Error flag
    } B;
    __I  uint32_t  R;

    explicit INTFR_DEF (volatile INTFR_DEF & o) noexcept { R = o.R; };
  };
  union INTFCR_DEF  {  //!< DMA interrupt flag clear register (DMA_INTFCR)
    struct {
      __O  ONE_BIT  CGIF1  :  1; //!<[00] Channel 1 Global interrupt clear
      __O  ONE_BIT  CTCIF1 :  1; //!<[01] Channel 1 Transfer Complete clear
      __O  ONE_BIT  CHTIF1 :  1; //!<[02] Channel 1 Half Transfer clear
      __O  ONE_BIT  CTEIF1 :  1; //!<[03] Channel 1 Transfer Error clear
      __O  ONE_BIT  CGIF2  :  1; //!<[04] Channel 2 Global interrupt clear
      __O  ONE_BIT  CTCIF2 :  1; //!<[05] Channel 2 Transfer Complete clear
      __O  ONE_BIT  CHTIF2 :  1; //!<[06] Channel 2 Half Transfer clear
      __O  ONE_BIT  CTEIF2 :  1; //!<[07] Channel 2 Transfer Error clear
      __O  ONE_BIT  CGIF3  :  1; //!<[08] Channel 3 Global interrupt clear
      __O  ONE_BIT  CTCIF3 :  1; //!<[09] Channel 3 Transfer Complete clear
      __O  ONE_BIT  CHTIF3 :  1; //!<[10] Channel 3 Half Transfer clear
      __O  ONE_BIT  CTEIF3 :  1; //!<[11] Channel 3 Transfer Error clear
      __O  ONE_BIT  CGIF4  :  1; //!<[12] Channel 4 Global interrupt clear
      __O  ONE_BIT  CTCIF4 :  1; //!<[13] Channel 4 Transfer Complete clear
      __O  ONE_BIT  CHTIF4 :  1; //!<[14] Channel 4 Half Transfer clear
      __O  ONE_BIT  CTEIF4 :  1; //!<[15] Channel 4 Transfer Error clear
      __O  ONE_BIT  CGIF5  :  1; //!<[16] Channel 5 Global interrupt clear
      __O  ONE_BIT  CTCIF5 :  1; //!<[17] Channel 5 Transfer Complete clear
      __O  ONE_BIT  CHTIF5 :  1; //!<[18] Channel 5 Half Transfer clear
      __O  ONE_BIT  CTEIF5 :  1; //!<[19] Channel 5 Transfer Error clear
      __O  ONE_BIT  CGIF6  :  1; //!<[20] Channel 6 Global interrupt clear
      __O  ONE_BIT  CTCIF6 :  1; //!<[21] Channel 6 Transfer Complete clear
      __O  ONE_BIT  CHTIF6 :  1; //!<[22] Channel 6 Half Transfer clear
      __O  ONE_BIT  CTEIF6 :  1; //!<[23] Channel 6 Transfer Error clear
      __O  ONE_BIT  CGIF7  :  1; //!<[24] Channel 7 Global interrupt clear
      __O  ONE_BIT  CTCIF7 :  1; //!<[25] Channel 7 Transfer Complete clear
      __O  ONE_BIT  CHTIF7 :  1; //!<[26] Channel 7 Half Transfer clear
      __O  ONE_BIT  CTEIF7 :  1; //!<[27] Channel 7 Transfer Error clear
    } B;
    __O  uint32_t  R;
    explicit INTFCR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      INTFCR_DEF r;
      R = f (r);
    }
  };
  union CFGR1_DEF   {  //!< DMA channel configuration register (DMA_CFGR)
    struct {
      __IO ONE_BIT    EN      :  1; //!<[00] Channel enable
      __IO ONE_BIT    TCIE    :  1; //!<[01] Transfer complete interrupt enable
      __IO ONE_BIT    HTIE    :  1; //!<[02] Half Transfer interrupt enable
      __IO ONE_BIT    TEIE    :  1; //!<[03] Transfer error interrupt enable
      __IO ONE_BIT    DIR     :  1; //!<[04] Data transfer direction
      __IO ONE_BIT    CIRC    :  1; //!<[05] Circular mode
      __IO ONE_BIT    PINC    :  1; //!<[06] Peripheral increment mode
      __IO ONE_BIT    MINC    :  1; //!<[07] Memory increment mode
      __IO uint32_t   PSIZE   :  2; //!<[08] Peripheral size
      __IO uint32_t   MSIZE   :  2; //!<[10] Memory size
      __IO uint32_t   PL      :  2; //!<[12] Channel Priority level
      __IO ONE_BIT    MEM2MEM :  1; //!<[14] Memory to memory mode
    } B;
    __IO uint32_t  R;
    explicit CFGR1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CFGR1_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CFGR1_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CNTR1_DEF   {  //!< DMA channel 1 number of data register
    struct {
      __IO uint32_t   NDT : 16; //!<[00] Number of data to transfer
    } B;
    __IO uint32_t  R;
    explicit CNTR1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CNTR1_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CNTR1_DEF r; r.R = R;
      R = f (r);
    }
  };
  union PADDR1_DEF  {  //!< DMA channel 1 peripheral address register
    struct {
      __IO uint32_t   PA : 32; //!<[00] Peripheral address
    } B;
    __IO uint32_t  R;
    explicit PADDR1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      PADDR1_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      PADDR1_DEF r; r.R = R;
      R = f (r);
    }
  };
  union MADDR1_DEF  {  //!< DMA channel 1 memory address register
    struct {
      __IO uint32_t   MA : 32; //!<[00] Memory address
    } B;
    __IO uint32_t  R;
    explicit MADDR1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      MADDR1_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      MADDR1_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CFGR2_DEF   {  //!< DMA channel configuration register (DMA_CFGR)
    struct {
      __IO ONE_BIT    EN      :  1; //!<[00] Channel enable
      __IO ONE_BIT    TCIE    :  1; //!<[01] Transfer complete interrupt enable
      __IO ONE_BIT    HTIE    :  1; //!<[02] Half Transfer interrupt enable
      __IO ONE_BIT    TEIE    :  1; //!<[03] Transfer error interrupt enable
      __IO ONE_BIT    DIR     :  1; //!<[04] Data transfer direction
      __IO ONE_BIT    CIRC    :  1; //!<[05] Circular mode
      __IO ONE_BIT    PINC    :  1; //!<[06] Peripheral increment mode
      __IO ONE_BIT    MINC    :  1; //!<[07] Memory increment mode
      __IO uint32_t   PSIZE   :  2; //!<[08] Peripheral size
      __IO uint32_t   MSIZE   :  2; //!<[10] Memory size
      __IO uint32_t   PL      :  2; //!<[12] Channel Priority level
      __IO ONE_BIT    MEM2MEM :  1; //!<[14] Memory to memory mode
    } B;
    __IO uint32_t  R;
    explicit CFGR2_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CFGR2_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CFGR2_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CNTR2_DEF   {  //!< DMA channel 2 number of data register
    struct {
      __IO uint32_t   NDT : 16; //!<[00] Number of data to transfer
    } B;
    __IO uint32_t  R;
    explicit CNTR2_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CNTR2_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CNTR2_DEF r; r.R = R;
      R = f (r);
    }
  };
  union PADDR2_DEF  {  //!< DMA channel 2 peripheral address register
    struct {
      __IO uint32_t   PA : 32; //!<[00] Peripheral address
    } B;
    __IO uint32_t  R;
    explicit PADDR2_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      PADDR2_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      PADDR2_DEF r; r.R = R;
      R = f (r);
    }
  };
  union MADDR2_DEF  {  //!< DMA channel 2 memory address register
    struct {
      __IO uint32_t   MA : 32; //!<[00] Memory address
    } B;
    __IO uint32_t  R;
    explicit MADDR2_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      MADDR2_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      MADDR2_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CFGR3_DEF   {  //!< DMA channel configuration register (DMA_CFGR)
    struct {
      __IO ONE_BIT    EN      :  1; //!<[00] Channel enable
      __IO ONE_BIT    TCIE    :  1; //!<[01] Transfer complete interrupt enable
      __IO ONE_BIT    HTIE    :  1; //!<[02] Half Transfer interrupt enable
      __IO ONE_BIT    TEIE    :  1; //!<[03] Transfer error interrupt enable
      __IO ONE_BIT    DIR     :  1; //!<[04] Data transfer direction
      __IO ONE_BIT    CIRC    :  1; //!<[05] Circular mode
      __IO ONE_BIT    PINC    :  1; //!<[06] Peripheral increment mode
      __IO ONE_BIT    MINC    :  1; //!<[07] Memory increment mode
      __IO uint32_t   PSIZE   :  2; //!<[08] Peripheral size
      __IO uint32_t   MSIZE   :  2; //!<[10] Memory size
      __IO uint32_t   PL      :  2; //!<[12] Channel Priority level
      __IO ONE_BIT    MEM2MEM :  1; //!<[14] Memory to memory mode
    } B;
    __IO uint32_t  R;
    explicit CFGR3_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CFGR3_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CFGR3_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CNTR3_DEF   {  //!< DMA channel 3 number of data register
    struct {
      __IO uint32_t   NDT : 16; //!<[00] Number of data to transfer
    } B;
    __IO uint32_t  R;
    explicit CNTR3_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CNTR3_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CNTR3_DEF r; r.R = R;
      R = f (r);
    }
  };
  union PADDR3_DEF  {  //!< DMA channel 3 peripheral address register
    struct {
      __IO uint32_t   PA : 32; //!<[00] Peripheral address
    } B;
    __IO uint32_t  R;
    explicit PADDR3_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      PADDR3_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      PADDR3_DEF r; r.R = R;
      R = f (r);
    }
  };
  union MADDR3_DEF  {  //!< DMA channel 3 memory address register
    struct {
      __IO uint32_t   MA : 32; //!<[00] Memory address
    } B;
    __IO uint32_t  R;
    explicit MADDR3_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      MADDR3_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      MADDR3_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CFGR4_DEF   {  //!< DMA channel configuration register (DMA_CFGR)
    struct {
      __IO ONE_BIT    EN      :  1; //!<[00] Channel enable
      __IO ONE_BIT    TCIE    :  1; //!<[01] Transfer complete interrupt enable
      __IO ONE_BIT    HTIE    :  1; //!<[02] Half Transfer interrupt enable
      __IO ONE_BIT    TEIE    :  1; //!<[03] Transfer error interrupt enable
      __IO ONE_BIT    DIR     :  1; //!<[04] Data transfer direction
      __IO ONE_BIT    CIRC    :  1; //!<[05] Circular mode
      __IO ONE_BIT    PINC    :  1; //!<[06] Peripheral increment mode
      __IO ONE_BIT    MINC    :  1; //!<[07] Memory increment mode
      __IO uint32_t   PSIZE   :  2; //!<[08] Peripheral size
      __IO uint32_t   MSIZE   :  2; //!<[10] Memory size
      __IO uint32_t   PL      :  2; //!<[12] Channel Priority level
      __IO ONE_BIT    MEM2MEM :  1; //!<[14] Memory to memory mode
    } B;
    __IO uint32_t  R;
    explicit CFGR4_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CFGR4_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CFGR4_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CNTR4_DEF   {  //!< DMA channel 4 number of data register
    struct {
      __IO uint32_t   NDT : 16; //!<[00] Number of data to transfer
    } B;
    __IO uint32_t  R;
    explicit CNTR4_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CNTR4_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CNTR4_DEF r; r.R = R;
      R = f (r);
    }
  };
  union PADDR4_DEF  {  //!< DMA channel 4 peripheral address register
    struct {
      __IO uint32_t   PA : 32; //!<[00] Peripheral address
    } B;
    __IO uint32_t  R;
    explicit PADDR4_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      PADDR4_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      PADDR4_DEF r; r.R = R;
      R = f (r);
    }
  };
  union MADDR4_DEF  {  //!< DMA channel 4 memory address register
    struct {
      __IO uint32_t   MA : 32; //!<[00] Memory address
    } B;
    __IO uint32_t  R;
    explicit MADDR4_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      MADDR4_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      MADDR4_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CFGR5_DEF   {  //!< DMA channel configuration register (DMA_CFGR)
    struct {
      __IO ONE_BIT    EN      :  1; //!<[00] Channel enable
      __IO ONE_BIT    TCIE    :  1; //!<[01] Transfer complete interrupt enable
      __IO ONE_BIT    HTIE    :  1; //!<[02] Half Transfer interrupt enable
      __IO ONE_BIT    TEIE    :  1; //!<[03] Transfer error interrupt enable
      __IO ONE_BIT    DIR     :  1; //!<[04] Data transfer direction
      __IO ONE_BIT    CIRC    :  1; //!<[05] Circular mode
      __IO ONE_BIT    PINC    :  1; //!<[06] Peripheral increment mode
      __IO ONE_BIT    MINC    :  1; //!<[07] Memory increment mode
      __IO uint32_t   PSIZE   :  2; //!<[08] Peripheral size
      __IO uint32_t   MSIZE   :  2; //!<[10] Memory size
      __IO uint32_t   PL      :  2; //!<[12] Channel Priority level
      __IO ONE_BIT    MEM2MEM :  1; //!<[14] Memory to memory mode
    } B;
    __IO uint32_t  R;
    explicit CFGR5_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CFGR5_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CFGR5_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CNTR5_DEF   {  //!< DMA channel 5 number of data register
    struct {
      __IO uint32_t   NDT : 16; //!<[00] Number of data to transfer
    } B;
    __IO uint32_t  R;
    explicit CNTR5_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CNTR5_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CNTR5_DEF r; r.R = R;
      R = f (r);
    }
  };
  union PADDR5_DEF  {  //!< DMA channel 5 peripheral address register
    struct {
      __IO uint32_t   PA : 32; //!<[00] Peripheral address
    } B;
    __IO uint32_t  R;
    explicit PADDR5_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      PADDR5_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      PADDR5_DEF r; r.R = R;
      R = f (r);
    }
  };
  union MADDR5_DEF  {  //!< DMA channel 5 memory address register
    struct {
      __IO uint32_t   MA : 32; //!<[00] Memory address
    } B;
    __IO uint32_t  R;
    explicit MADDR5_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      MADDR5_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      MADDR5_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CFGR6_DEF   {  //!< DMA channel configuration register (DMA_CFGR)
    struct {
      __IO ONE_BIT    EN      :  1; //!<[00] Channel enable
      __IO ONE_BIT    TCIE    :  1; //!<[01] Transfer complete interrupt enable
      __IO ONE_BIT    HTIE    :  1; //!<[02] Half Transfer interrupt enable
      __IO ONE_BIT    TEIE    :  1; //!<[03] Transfer error interrupt enable
      __IO ONE_BIT    DIR     :  1; //!<[04] Data transfer direction
      __IO ONE_BIT    CIRC    :  1; //!<[05] Circular mode
      __IO ONE_BIT    PINC    :  1; //!<[06] Peripheral increment mode
      __IO ONE_BIT    MINC    :  1; //!<[07] Memory increment mode
      __IO uint32_t   PSIZE   :  2; //!<[08] Peripheral size
      __IO uint32_t   MSIZE   :  2; //!<[10] Memory size
      __IO uint32_t   PL      :  2; //!<[12] Channel Priority level
      __IO ONE_BIT    MEM2MEM :  1; //!<[14] Memory to memory mode
    } B;
    __IO uint32_t  R;
    explicit CFGR6_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CFGR6_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CFGR6_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CNTR6_DEF   {  //!< DMA channel 6 number of data register
    struct {
      __IO uint32_t   NDT : 16; //!<[00] Number of data to transfer
    } B;
    __IO uint32_t  R;
    explicit CNTR6_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CNTR6_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CNTR6_DEF r; r.R = R;
      R = f (r);
    }
  };
  union PADDR6_DEF  {  //!< DMA channel 6 peripheral address register
    struct {
      __IO uint32_t   PA : 32; //!<[00] Peripheral address
    } B;
    __IO uint32_t  R;
    explicit PADDR6_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      PADDR6_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      PADDR6_DEF r; r.R = R;
      R = f (r);
    }
  };
  union MADDR6_DEF  {  //!< DMA channel 6 memory address register
    struct {
      __IO uint32_t   MA : 32; //!<[00] Memory address
    } B;
    __IO uint32_t  R;
    explicit MADDR6_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      MADDR6_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      MADDR6_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CFGR7_DEF   {  //!< DMA channel configuration register (DMA_CFGR)
    struct {
      __IO ONE_BIT    EN      :  1; //!<[00] Channel enable
      __IO ONE_BIT    TCIE    :  1; //!<[01] Transfer complete interrupt enable
      __IO ONE_BIT    HTIE    :  1; //!<[02] Half Transfer interrupt enable
      __IO ONE_BIT    TEIE    :  1; //!<[03] Transfer error interrupt enable
      __IO ONE_BIT    DIR     :  1; //!<[04] Data transfer direction
      __IO ONE_BIT    CIRC    :  1; //!<[05] Circular mode
      __IO ONE_BIT    PINC    :  1; //!<[06] Peripheral increment mode
      __IO ONE_BIT    MINC    :  1; //!<[07] Memory increment mode
      __IO uint32_t   PSIZE   :  2; //!<[08] Peripheral size
      __IO uint32_t   MSIZE   :  2; //!<[10] Memory size
      __IO uint32_t   PL      :  2; //!<[12] Channel Priority level
      __IO ONE_BIT    MEM2MEM :  1; //!<[14] Memory to memory mode
    } B;
    __IO uint32_t  R;
    explicit CFGR7_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CFGR7_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CFGR7_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CNTR7_DEF   {  //!< DMA channel 7 number of data register
    struct {
      __IO uint32_t   NDT : 16; //!<[00] Number of data to transfer
    } B;
    __IO uint32_t  R;
    explicit CNTR7_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CNTR7_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CNTR7_DEF r; r.R = R;
      R = f (r);
    }
  };
  union PADDR7_DEF  {  //!< DMA channel 7 peripheral address register
    struct {
      __IO uint32_t   PA : 32; //!<[00] Peripheral address
    } B;
    __IO uint32_t  R;
    explicit PADDR7_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      PADDR7_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      PADDR7_DEF r; r.R = R;
      R = f (r);
    }
  };
  union MADDR7_DEF  {  //!< DMA channel 7 memory address register
    struct {
      __IO uint32_t   MA : 32; //!<[00] Memory address
    } B;
    __IO uint32_t  R;
    explicit MADDR7_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      MADDR7_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      MADDR7_DEF r; r.R = R;
      R = f (r);
    }
  };
  // PERIPHERAL DMA1 REGISTERS INSTANCES
  __I  INTFR_DEF             INTFR ;  //!< [0000](04)[0x00000000]
  __O  INTFCR_DEF           INTFCR ;  //!< [0004](04)[0x00000000]
  __IO CFGR1_DEF             CFGR1 ;  //!< [0008](04)[0x00000000]
  __IO CNTR1_DEF             CNTR1 ;  //!< [000c](04)[0x00000000]
  __IO PADDR1_DEF           PADDR1 ;  //!< [0010](04)[0x00000000]
  __IO MADDR1_DEF           MADDR1 ;  //!< [0014](04)[0x00000000]
       uint32_t          UNUSED0 ;  //!< [0018](04)[0xFFFFFFFF]
  __IO CFGR2_DEF             CFGR2 ;  //!< [001c](04)[0x00000000]
  __IO CNTR2_DEF             CNTR2 ;  //!< [0020](04)[0x00000000]
  __IO PADDR2_DEF           PADDR2 ;  //!< [0024](04)[0x00000000]
  __IO MADDR2_DEF           MADDR2 ;  //!< [0028](04)[0x00000000]
       uint32_t          UNUSED1 ;  //!< [002c](04)[0xFFFFFFFF]
  __IO CFGR3_DEF             CFGR3 ;  //!< [0030](04)[0x00000000]
  __IO CNTR3_DEF             CNTR3 ;  //!< [0034](04)[0x00000000]
  __IO PADDR3_DEF           PADDR3 ;  //!< [0038](04)[0x00000000]
  __IO MADDR3_DEF           MADDR3 ;  //!< [003c](04)[0x00000000]
       uint32_t          UNUSED2 ;  //!< [0040](04)[0xFFFFFFFF]
  __IO CFGR4_DEF             CFGR4 ;  //!< [0044](04)[0x00000000]
  __IO CNTR4_DEF             CNTR4 ;  //!< [0048](04)[0x00000000]
  __IO PADDR4_DEF           PADDR4 ;  //!< [004c](04)[0x00000000]
  __IO MADDR4_DEF           MADDR4 ;  //!< [0050](04)[0x00000000]
       uint32_t          UNUSED3 ;  //!< [0054](04)[0xFFFFFFFF]
  __IO CFGR5_DEF             CFGR5 ;  //!< [0058](04)[0x00000000]
  __IO CNTR5_DEF             CNTR5 ;  //!< [005c](04)[0x00000000]
  __IO PADDR5_DEF           PADDR5 ;  //!< [0060](04)[0x00000000]
  __IO MADDR5_DEF           MADDR5 ;  //!< [0064](04)[0x00000000]
       uint32_t          UNUSED4 ;  //!< [0068](04)[0xFFFFFFFF]
  __IO CFGR6_DEF             CFGR6 ;  //!< [006c](04)[0x00000000]
  __IO CNTR6_DEF             CNTR6 ;  //!< [0070](04)[0x00000000]
  __IO PADDR6_DEF           PADDR6 ;  //!< [0074](04)[0x00000000]
  __IO MADDR6_DEF           MADDR6 ;  //!< [0078](04)[0x00000000]
       uint32_t          UNUSED5 ;  //!< [007c](04)[0xFFFFFFFF]
  __IO CFGR7_DEF             CFGR7 ;  //!< [0080](04)[0x00000000]
  __IO CNTR7_DEF             CNTR7 ;  //!< [0084](04)[0x00000000]
  __IO PADDR7_DEF           PADDR7 ;  //!< [0088](04)[0x00000000]
  __IO MADDR7_DEF           MADDR7 ;  //!< [008c](04)[0x00000000]
}; /* total size = 0x0400, struct size = 0x0090 */

// ////////////////////+++ IWDG +-+//////////////////// //
struct IWDG_Type   { /*!< Independent watchdog */
  union CTLR_DEF  {  //!< Key register (IWDG_CTLR)
    struct {
      __O  uint32_t   KEY : 16; //!<[00] Key value
    } B;
    __O  uint32_t  R;
    explicit CTLR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CTLR_DEF r;
      R = f (r);
    }
  };
  union PSCR_DEF  {  //!< Prescaler register (IWDG_PSCR)
    struct {
      __IO uint32_t   PR :  3; //!<[00] Prescaler divider
    } B;
    __IO uint32_t  R;
    explicit PSCR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      PSCR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      PSCR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union RLDR_DEF  {  //!< Reload register (IWDG_RLDR)
    struct {
      __IO uint32_t   RL : 12; //!<[00] Watchdog counter reload value
    } B;
    __IO uint32_t  R;
    explicit RLDR_DEF () noexcept { R = 0x00000fffu; }
    template<typename F> void setbit (F f) volatile {
      RLDR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      RLDR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union STATR_DEF {  //!< Status register (IWDG_SR)
    struct {
      __I  ONE_BIT  PVU :  1; //!<[00] Watchdog prescaler value update
      __I  ONE_BIT  RVU :  1; //!<[01] Watchdog counter reload value update
    } B;
    __I  uint32_t  R;

    explicit STATR_DEF (volatile STATR_DEF & o) noexcept { R = o.R; };
  };
  // PERIPHERAL IWDG REGISTERS INSTANCES
  __O  CTLR_DEF             CTLR ;  //!< [0000](04)[0x00000000]
  __IO PSCR_DEF             PSCR ;  //!< [0004](04)[0x00000000]
  __IO RLDR_DEF             RLDR ;  //!< [0008](04)[0x00000FFF]
  __I  STATR_DEF           STATR ;  //!< [000c](04)[0x00000000]
}; /* total size = 0x0400, struct size = 0x0010 */

// ////////////////////+++ WWDG +-+//////////////////// //
struct WWDG_Type   { /*!< Window watchdog */
  union CTLR_DEF  {  //!< Control register (WWDG_CR)
    struct {
      __IO uint32_t   T    :  7; //!<[00] 7-bit counter (MSB to LSB)
      __IO ONE_BIT    WDGA :  1; //!<[07] Activation bit
    } B;
    __IO uint32_t  R;
    explicit CTLR_DEF () noexcept { R = 0x0000007fu; }
    template<typename F> void setbit (F f) volatile {
      CTLR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CTLR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CFGR_DEF  {  //!< Configuration register (WWDG_CFR)
    struct {
      __IO uint32_t   W     :  7; //!<[00] 7-bit window value
      __IO uint32_t   WDGTB :  2; //!<[07] Timer Base
      __IO ONE_BIT    EWI   :  1; //!<[09] Early Wakeup Interrupt
    } B;
    __IO uint32_t  R;
    explicit CFGR_DEF () noexcept { R = 0x0000007fu; }
    template<typename F> void setbit (F f) volatile {
      CFGR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CFGR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union STATR_DEF {  //!< Status register (WWDG_SR)
    struct {
      __IO ONE_BIT  WEIF :  1; //!<[00] Early Wakeup Interrupt Flag
    } B;
    __IO uint32_t  R;
    explicit STATR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      STATR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      STATR_DEF r; r.R = R;
      R = f (r);
    }
  };
  // PERIPHERAL WWDG REGISTERS INSTANCES
  __IO CTLR_DEF             CTLR ;  //!< [0000](04)[0x0000007F]
  __IO CFGR_DEF             CFGR ;  //!< [0004](04)[0x0000007F]
  __IO STATR_DEF           STATR ;  //!< [0008](04)[0x00000000]
}; /* total size = 0x0400, struct size = 0x000C */

// ////////////////////+++ TIM1 +-+//////////////////// //
struct TIM1_Type   { /*!< Advanced timer */
  union CTLR1_DEF          {  //!< control register 1
    struct {
      __IO ONE_BIT    CEN            :  1; //!<[00] Counter enable
      __IO ONE_BIT    UDIS           :  1; //!<[01] Update disable
      __IO ONE_BIT    URS            :  1; //!<[02] Update request source
      __IO ONE_BIT    OPM            :  1; //!<[03] One-pulse mode
      __IO ONE_BIT    DIR            :  1; //!<[04] Direction
      __IO uint32_t   CMS            :  2; //!<[05] Center-aligned mode selection
      __IO ONE_BIT    ARPE           :  1; //!<[07] Auto-reload preload enable
      __IO uint32_t   CKD            :  2; //!<[08] Clock division
           uint32_t   UNUSED0        :  4; //!<[10] 
      __IO ONE_BIT    TMR_CAP_OV_EN  :  1; //!<[14] Timer capture value configuration enable
      __IO ONE_BIT    TMR_CAP_LVL_EN :  1; //!<[15] Timer capture level indication enable
    } B;
    __IO uint32_t  R;
    explicit CTLR1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CTLR1_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CTLR1_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CTLR2_DEF          {  //!< control register 2
    struct {
      __IO ONE_BIT    CCPC    :  1; //!<[00] Capture/compare preloaded control
           ONE_BIT    UNUSED0 :  1; //!<[01] 
      __IO ONE_BIT    CCUS    :  1; //!<[02] Capture/compare control update selection
      __IO ONE_BIT    CCDS    :  1; //!<[03] Capture/compare DMA selection
      __IO uint32_t   MMS     :  3; //!<[04] Master mode selection
      __IO ONE_BIT    TI1S    :  1; //!<[07] TI1 selection
      __IO ONE_BIT    OIS1    :  1; //!<[08] Output Idle state 1
      __IO ONE_BIT    OIS1N   :  1; //!<[09] Output Idle state 1
      __IO ONE_BIT    OIS2    :  1; //!<[10] Output Idle state 2
      __IO ONE_BIT    OIS2N   :  1; //!<[11] Output Idle state 2
      __IO ONE_BIT    OIS3    :  1; //!<[12] Output Idle state 3
      __IO ONE_BIT    OIS3N   :  1; //!<[13] Output Idle state 3
      __IO ONE_BIT    OIS4    :  1; //!<[14] Output Idle state 4
    } B;
    __IO uint32_t  R;
    explicit CTLR2_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CTLR2_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CTLR2_DEF r; r.R = R;
      R = f (r);
    }
  };
  union SMCFGR_DEF         {  //!< slave mode control register
    struct {
      __IO uint32_t   SMS     :  3; //!<[00] Slave mode selection
           ONE_BIT    UNUSED0 :  1; //!<[03] 
      __IO uint32_t   TS      :  3; //!<[04] Trigger selection
      __IO ONE_BIT    MSM     :  1; //!<[07] Master/Slave mode
      __IO uint32_t   ETF     :  4; //!<[08] External trigger filter
      __IO uint32_t   ETPS    :  2; //!<[12] External trigger prescaler
      __IO ONE_BIT    ECE     :  1; //!<[14] External clock enable
      __I  ONE_BIT    ETP     :  1; //!<[15] External trigger polarity
    } B;
    __IO uint32_t  R;
    explicit SMCFGR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      SMCFGR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      SMCFGR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union DMAINTENR_DEF      {  //!< DMA/Interrupt enable register
    struct {
      __IO ONE_BIT  UIE   :  1; //!<[00] Update interrupt enable
      __IO ONE_BIT  CC1IE :  1; //!<[01] Capture/Compare 1 interrupt enable
      __IO ONE_BIT  CC2IE :  1; //!<[02] Capture/Compare 2 interrupt enable
      __IO ONE_BIT  CC3IE :  1; //!<[03] Capture/Compare 3 interrupt enable
      __IO ONE_BIT  CC4IE :  1; //!<[04] Capture/Compare 4 interrupt enable
      __IO ONE_BIT  COMIE :  1; //!<[05] COM interrupt enable
      __IO ONE_BIT  TIE   :  1; //!<[06] Trigger interrupt enable
      __IO ONE_BIT  BIE   :  1; //!<[07] Break interrupt enable
      __IO ONE_BIT  UDE   :  1; //!<[08] Update DMA request enable
      __IO ONE_BIT  CC1DE :  1; //!<[09] Capture/Compare 1 DMA request enable
      __IO ONE_BIT  CC2DE :  1; //!<[10] Capture/Compare 2 DMA request enable
      __IO ONE_BIT  CC3DE :  1; //!<[11] Capture/Compare 3 DMA request enable
      __IO ONE_BIT  CC4DE :  1; //!<[12] Capture/Compare 4 DMA request enable
      __IO ONE_BIT  COMDE :  1; //!<[13] COM DMA request enable
      __IO ONE_BIT  TDE   :  1; //!<[14] Trigger DMA request enable
    } B;
    __IO uint32_t  R;
    explicit DMAINTENR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      DMAINTENR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      DMAINTENR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union INTFR_DEF          {  //!< status register
    struct {
      __IO ONE_BIT  UIF     :  1; //!<[00] Update interrupt flag
      __IO ONE_BIT  CC1IF   :  1; //!<[01] Capture/compare 1 interrupt flag
      __IO ONE_BIT  CC2IF   :  1; //!<[02] Capture/Compare 2 interrupt flag
      __IO ONE_BIT  CC3IF   :  1; //!<[03] Capture/Compare 3 interrupt flag
      __IO ONE_BIT  CC4IF   :  1; //!<[04] Capture/Compare 4 interrupt flag
      __IO ONE_BIT  COMIF   :  1; //!<[05] COM interrupt flag
      __IO ONE_BIT  TIF     :  1; //!<[06] Trigger interrupt flag
      __IO ONE_BIT  BIF     :  1; //!<[07] Break interrupt flag
           ONE_BIT  UNUSED0 :  1; //!<[08] 
      __IO ONE_BIT  CC1OF   :  1; //!<[09] Capture/Compare 1 overcapture flag
      __IO ONE_BIT  CC2OF   :  1; //!<[10] Capture/compare 2 overcapture flag
      __IO ONE_BIT  CC3OF   :  1; //!<[11] Capture/Compare 3 overcapture flag
      __IO ONE_BIT  CC4OF   :  1; //!<[12] Capture/Compare 4 overcapture flag
    } B;
    __IO uint32_t  R;
    explicit INTFR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      INTFR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      INTFR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union SWEVGR_DEF         {  //!< event generation register
    struct {
      __O  ONE_BIT  UG   :  1; //!<[00] Update generation
      __O  ONE_BIT  CC1G :  1; //!<[01] Capture/compare 1 generation
      __O  ONE_BIT  CC2G :  1; //!<[02] Capture/compare 2 generation
      __O  ONE_BIT  CC3G :  1; //!<[03] Capture/compare 3 generation
      __O  ONE_BIT  CC4G :  1; //!<[04] Capture/compare 4 generation
      __O  ONE_BIT  COMG :  1; //!<[05] Capture/Compare control update generation
      __O  ONE_BIT  TG   :  1; //!<[06] Trigger generation
      __O  ONE_BIT  BG   :  1; //!<[07] Break generation
    } B;
    __O  uint32_t  R;
    explicit SWEVGR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      SWEVGR_DEF r;
      R = f (r);
    }
  };
  union CHCTLR1_Input_DEF  {  //!< capture/compare mode register 1 (input mode)
    struct {
      __IO uint32_t   CC1S   :  2; //!<[00] Capture/Compare 1 selection
      __IO uint32_t   IC1PSC :  2; //!<[02] Input capture 1 prescaler
      __IO uint32_t   IC1F   :  4; //!<[04] Input capture 1 filter
      __IO uint32_t   CC2S   :  2; //!<[08] Capture/Compare 2 selection
      __IO uint32_t   IC2PCS :  2; //!<[10] Input capture 2 prescaler
      __IO uint32_t   IC2F   :  4; //!<[12] Input capture 2 filter
    } B;
    __IO uint32_t  R;
    explicit CHCTLR1_Input_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CHCTLR1_Input_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CHCTLR1_Input_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CHCTLR1_Output_DEF {  //!< capture/compare mode register (output mode)
    struct {
      __IO uint32_t   CC1S  :  2; //!<[00] Capture/Compare 1 selection
      __IO ONE_BIT    OC1FE :  1; //!<[02] Output Compare 1 fast enable
      __IO ONE_BIT    OC1PE :  1; //!<[03] Output Compare 1 preload enable
      __IO uint32_t   OC1M  :  3; //!<[04] Output Compare 1 mode
      __IO ONE_BIT    OC1CE :  1; //!<[07] Output Compare 1 clear enable
      __IO uint32_t   CC2S  :  2; //!<[08] Capture/Compare 2 selection
      __IO ONE_BIT    OC2FE :  1; //!<[10] Output Compare 2 fast enable
      __IO ONE_BIT    OC2PE :  1; //!<[11] Output Compare 2 preload enable
      __IO uint32_t   OC2M  :  3; //!<[12] Output Compare 2 mode
      __IO ONE_BIT    OC2CE :  1; //!<[15] Output Compare 2 clear enable
    } B;
    __IO uint32_t  R;
    explicit CHCTLR1_Output_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CHCTLR1_Output_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CHCTLR1_Output_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CHCTLR2_Output_DEF {  //!< capture/compare mode register (output mode)
    struct {
      __IO uint32_t   CC3S  :  2; //!<[00] Capture/Compare 3 selection
      __IO ONE_BIT    OC3FE :  1; //!<[02] Output compare 3 fast enable
      __IO ONE_BIT    OC3PE :  1; //!<[03] Output compare 3 preload enable
      __IO uint32_t   OC3M  :  3; //!<[04] Output compare 3 mode
      __IO ONE_BIT    OC3CE :  1; //!<[07] Output compare 3 clear enable
      __IO uint32_t   CC4S  :  2; //!<[08] Capture/Compare 4 selection
      __IO ONE_BIT    OC4FE :  1; //!<[10] Output compare 4 fast enable
      __IO ONE_BIT    OC4PE :  1; //!<[11] Output compare 4 preload enable
      __IO uint32_t   OC4M  :  3; //!<[12] Output compare 4 mode
      __IO ONE_BIT    OC4CE :  1; //!<[15] Output compare 4 clear enable
    } B;
    __IO uint32_t  R;
    explicit CHCTLR2_Output_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CHCTLR2_Output_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CHCTLR2_Output_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CHCTLR2_Input_DEF  {  //!< capture/compare mode register 2 (input mode)
    struct {
      __IO uint32_t   CC3S   :  2; //!<[00] Capture/compare 3 selection
      __IO uint32_t   IC3PSC :  2; //!<[02] Input capture 3 prescaler
      __IO uint32_t   IC3F   :  4; //!<[04] Input capture 3 filter
      __IO uint32_t   CC4S   :  2; //!<[08] Capture/Compare 4 selection
      __IO uint32_t   IC4PSC :  2; //!<[10] Input capture 4 prescaler
      __IO uint32_t   IC4F   :  4; //!<[12] Input capture 4 filter
    } B;
    __IO uint32_t  R;
    explicit CHCTLR2_Input_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CHCTLR2_Input_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CHCTLR2_Input_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CCER_DEF           {  //!< capture/compare enable register
    struct {
      __IO ONE_BIT  CC1E  :  1; //!<[00] Capture/Compare 1 output enable
      __IO ONE_BIT  CC1P  :  1; //!<[01] Capture/Compare 1 output Polarity
      __IO ONE_BIT  CC1NE :  1; //!<[02] Capture/Compare 1 complementary output enable
      __IO ONE_BIT  CC1NP :  1; //!<[03] Capture/Compare 1 output Polarity
      __IO ONE_BIT  CC2E  :  1; //!<[04] Capture/Compare 2 output enable
      __IO ONE_BIT  CC2P  :  1; //!<[05] Capture/Compare 2 output Polarity
      __IO ONE_BIT  CC2NE :  1; //!<[06] Capture/Compare 2 complementary output enable
      __IO ONE_BIT  CC2NP :  1; //!<[07] Capture/Compare 2 output Polarity
      __IO ONE_BIT  CC3E  :  1; //!<[08] Capture/Compare 3 output enable
      __IO ONE_BIT  CC3P  :  1; //!<[09] Capture/Compare 3 output Polarity
      __IO ONE_BIT  CC3NE :  1; //!<[10] Capture/Compare 3 complementary output enable
      __IO ONE_BIT  CC3NP :  1; //!<[11] Capture/Compare 3 output Polarity
      __IO ONE_BIT  CC4E  :  1; //!<[12] Capture/Compare 4 output enable
      __IO ONE_BIT  CC4P  :  1; //!<[13] Capture/Compare 3 output Polarity
    } B;
    __IO uint32_t  R;
    explicit CCER_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CCER_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CCER_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CNT_DEF            {  //!< counter
    struct {
      __IO uint32_t   CNT : 16; //!<[00] counter value
    } B;
    __IO uint32_t  R;
    explicit CNT_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CNT_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CNT_DEF r; r.R = R;
      R = f (r);
    }
  };
  union PSC_DEF            {  //!< prescaler
    struct {
      __IO uint32_t   PSC : 16; //!<[00] Prescaler value
    } B;
    __IO uint32_t  R;
    explicit PSC_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      PSC_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      PSC_DEF r; r.R = R;
      R = f (r);
    }
  };
  union ATRLR_DEF          {  //!< auto-reload register
    struct {
      __IO uint32_t   ATRLR : 16; //!<[00] Auto-reload value
    } B;
    __IO uint32_t  R;
    explicit ATRLR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      ATRLR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      ATRLR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union RPTCR_DEF          {  //!< repetition counter register
    struct {
      __IO uint32_t   RPTCR :  8; //!<[00] Repetition counter value
    } B;
    __IO uint32_t  R;
    explicit RPTCR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      RPTCR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      RPTCR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CH1CVR_DEF         {  //!< capture/compare register 1
    struct {
      __IO uint32_t   CH1CVR : 16; //!<[00] Capture/Compare 1 value
    } B;
    __IO uint32_t  R;
    explicit CH1CVR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CH1CVR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CH1CVR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CH2CVR_DEF         {  //!< capture/compare register 2
    struct {
      __IO uint32_t   CH2CVR : 16; //!<[00] Capture/Compare 2 value
    } B;
    __IO uint32_t  R;
    explicit CH2CVR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CH2CVR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CH2CVR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CH3CVR_DEF         {  //!< capture/compare register 3
    struct {
      __IO uint32_t   CH3CVR : 16; //!<[00] Capture/Compare value
    } B;
    __IO uint32_t  R;
    explicit CH3CVR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CH3CVR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CH3CVR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CH4CVR_DEF         {  //!< capture/compare register 4
    struct {
      __IO uint32_t   CH4CVR : 16; //!<[00] Capture/Compare value
    } B;
    __IO uint32_t  R;
    explicit CH4CVR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CH4CVR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CH4CVR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union BDTR_DEF           {  //!< break and dead-time register
    struct {
      __IO uint32_t   DTG  :  8; //!<[00] Dead-time generator setup
      __IO uint32_t   LOCK :  2; //!<[08] Lock configuration
      __IO ONE_BIT    OSSI :  1; //!<[10] Off-state selection for Idle mode
      __IO ONE_BIT    OSSR :  1; //!<[11] Off-state selection for Run mode
      __IO ONE_BIT    BKE  :  1; //!<[12] Break enable
      __IO ONE_BIT    BKP  :  1; //!<[13] Break polarity
      __IO ONE_BIT    AOE  :  1; //!<[14] Automatic output enable
      __IO ONE_BIT    MOE  :  1; //!<[15] Main output enable
    } B;
    __IO uint32_t  R;
    explicit BDTR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      BDTR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      BDTR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union DMACFGR_DEF        {  //!< DMA control register
    struct {
      __IO uint32_t   DBA     :  5; //!<[00] DMA base address
           uint32_t   UNUSED0 :  3; //!<[05] 
      __IO uint32_t   DBL     :  5; //!<[08] DMA burst length
    } B;
    __IO uint32_t  R;
    explicit DMACFGR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      DMACFGR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      DMACFGR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union DMAADR_DEF         {  //!< DMA address for full transfer
    struct {
      __IO uint32_t   DMAADR : 16; //!<[00] DMA register for burst accesses
    } B;
    __IO uint32_t  R;
    explicit DMAADR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      DMAADR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      DMAADR_DEF r; r.R = R;
      R = f (r);
    }
  };
  // PERIPHERAL TIM1 REGISTERS INSTANCES
  __IO CTLR1_DEF                    CTLR1 ;  //!< [0000](04)[0x00000000]
  __IO CTLR2_DEF                    CTLR2 ;  //!< [0004](04)[0x00000000]
  __IO SMCFGR_DEF                  SMCFGR ;  //!< [0008](04)[0x00000000]
  __IO DMAINTENR_DEF            DMAINTENR ;  //!< [000c](04)[0x00000000]
  __IO INTFR_DEF                    INTFR ;  //!< [0010](04)[0x00000000]
  __O  SWEVGR_DEF                  SWEVGR ;  //!< [0014](04)[0x00000000]
  MERGE {
  __IO CHCTLR1_Input_DEF    CHCTLR1_Input ;  //!< [0018](04)[0x00000000]
  __IO CHCTLR1_Output_DEF  CHCTLR1_Output ;  //!< [0018](04)[0x00000000]
  };
  MERGE {
  __IO CHCTLR2_Output_DEF  CHCTLR2_Output ;  //!< [001c](04)[0x00000000]
  __IO CHCTLR2_Input_DEF    CHCTLR2_Input ;  //!< [001c](04)[0x00000000]
  };
  __IO CCER_DEF                      CCER ;  //!< [0020](04)[0x00000000]
  __IO CNT_DEF                        CNT ;  //!< [0024](04)[0x00000000]
  __IO PSC_DEF                        PSC ;  //!< [0028](04)[0x00000000]
  __IO ATRLR_DEF                    ATRLR ;  //!< [002c](04)[0x00000000]
  __IO RPTCR_DEF                    RPTCR ;  //!< [0030](04)[0x00000000]
  __IO CH1CVR_DEF                  CH1CVR ;  //!< [0034](04)[0x00000000]
  __IO CH2CVR_DEF                  CH2CVR ;  //!< [0038](04)[0x00000000]
  __IO CH3CVR_DEF                  CH3CVR ;  //!< [003c](04)[0x00000000]
  __IO CH4CVR_DEF                  CH4CVR ;  //!< [0040](04)[0x00000000]
  __IO BDTR_DEF                      BDTR ;  //!< [0044](04)[0x00000000]
  __IO DMACFGR_DEF                DMACFGR ;  //!< [0048](04)[0x00000000]
  __IO DMAADR_DEF                  DMAADR ;  //!< [004c](04)[0x00000000]
}; /* total size = 0x0400, struct size = 0x0050 */

// ////////////////////+++ TIM2 +-+//////////////////// //
struct TIM2_Type   { /*!< General purpose timer */
  union CTLR1_DEF         {  //!< control register 1
    struct {
      __IO ONE_BIT    CEN            :  1; //!<[00] Counter enable
      __IO ONE_BIT    UDIS           :  1; //!<[01] Update disable
      __IO ONE_BIT    URS            :  1; //!<[02] Update request source
      __IO ONE_BIT    OPM            :  1; //!<[03] One-pulse mode
      __IO ONE_BIT    DIR            :  1; //!<[04] Direction
      __IO uint32_t   CMS            :  2; //!<[05] Center-aligned mode selection
      __IO ONE_BIT    ARPE           :  1; //!<[07] Auto-reload preload enable
      __IO uint32_t   CKD            :  2; //!<[08] Clock division
           uint32_t   UNUSED0        :  4; //!<[10] 
      __IO ONE_BIT    TMR_CAP_OV_EN  :  1; //!<[14] Timer capture value configuration enable
      __IO ONE_BIT    TMR_CAP_LVL_EN :  1; //!<[15] Timer capture level indication enable
    } B;
    __IO uint32_t  R;
    explicit CTLR1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CTLR1_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CTLR1_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CTLR2_DEF         {  //!< control register 2
    struct {
           uint32_t   UNUSED0 :  3; //!<[00] 
      __IO ONE_BIT    CCDS    :  1; //!<[03] Capture/compare DMA selection
      __IO uint32_t   MMS     :  3; //!<[04] Master mode selection
      __IO ONE_BIT    TI1S    :  1; //!<[07] TI1 selection
    } B;
    __IO uint32_t  R;
    explicit CTLR2_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CTLR2_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CTLR2_DEF r; r.R = R;
      R = f (r);
    }
  };
  union SMCFGR_DEF        {  //!< slave mode control register
    struct {
      __IO uint32_t   SMS     :  3; //!<[00] Slave mode selection
           ONE_BIT    UNUSED0 :  1; //!<[03] 
      __IO uint32_t   TS      :  3; //!<[04] Trigger selection
      __IO ONE_BIT    MSM     :  1; //!<[07] Master/Slave mode
      __IO uint32_t   ETF     :  4; //!<[08] External trigger filter
      __IO uint32_t   ETPS    :  2; //!<[12] External trigger prescaler
      __IO ONE_BIT    ECE     :  1; //!<[14] External clock enable
      __IO ONE_BIT    ETP     :  1; //!<[15] External trigger polarity
    } B;
    __IO uint32_t  R;
    explicit SMCFGR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      SMCFGR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      SMCFGR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union DMAINTENR_DEF     {  //!< DMA/Interrupt enable register
    struct {
      __IO ONE_BIT  UIE     :  1; //!<[00] Update interrupt enable
      __IO ONE_BIT  CC1IE   :  1; //!<[01] Capture/Compare 1 interrupt enable
      __IO ONE_BIT  CC2IE   :  1; //!<[02] Capture/Compare 2 interrupt enable
      __IO ONE_BIT  CC3IE   :  1; //!<[03] Capture/Compare 3 interrupt enable
      __IO ONE_BIT  CC4IE   :  1; //!<[04] Capture/Compare 4 interrupt enable
           ONE_BIT  UNUSED0 :  1; //!<[05] 
      __IO ONE_BIT  TIE     :  1; //!<[06] Trigger interrupt enable
           ONE_BIT  UNUSED1 :  1; //!<[07] 
      __IO ONE_BIT  UDE     :  1; //!<[08] Update DMA request enable
      __IO ONE_BIT  CC1DE   :  1; //!<[09] Capture/Compare 1 DMA request enable
      __IO ONE_BIT  CC2DE   :  1; //!<[10] Capture/Compare 2 DMA request enable
      __IO ONE_BIT  CC3DE   :  1; //!<[11] Capture/Compare 3 DMA request enable
      __IO ONE_BIT  CC4DE   :  1; //!<[12] Capture/Compare 4 DMA request enable
           ONE_BIT  UNUSED2 :  1; //!<[13] 
      __IO ONE_BIT  TDE     :  1; //!<[14] Trigger DMA request enable
    } B;
    __IO uint32_t  R;
    explicit DMAINTENR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      DMAINTENR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      DMAINTENR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union INTFR_DEF         {  //!< status register
    struct {
      __IO ONE_BIT    UIF     :  1; //!<[00] Update interrupt flag
      __IO ONE_BIT    CC1IF   :  1; //!<[01] Capture/compare 1 interrupt flag
      __IO ONE_BIT    CC2IF   :  1; //!<[02] Capture/Compare 2 interrupt flag
      __IO ONE_BIT    CC3IF   :  1; //!<[03] Capture/Compare 3 interrupt flag
      __IO ONE_BIT    CC4IF   :  1; //!<[04] Capture/Compare 4 interrupt flag
           ONE_BIT    UNUSED0 :  1; //!<[05] 
      __IO ONE_BIT    TIF     :  1; //!<[06] Trigger interrupt flag
           uint32_t   UNUSED1 :  2; //!<[07] 
      __IO ONE_BIT    CC1OF   :  1; //!<[09] Capture/Compare 1 overcapture flag
      __IO ONE_BIT    CC2OF   :  1; //!<[10] Capture/compare 2 overcapture flag
      __IO ONE_BIT    CC3OF   :  1; //!<[11] Capture/Compare 3 overcapture flag
      __IO ONE_BIT    CC4OF   :  1; //!<[12] Capture/Compare 4 overcapture flag
    } B;
    __IO uint32_t  R;
    explicit INTFR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      INTFR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      INTFR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union SWEVGR_DEF        {  //!< event generation register
    struct {
      __O  ONE_BIT  UG      :  1; //!<[00] Update generation
      __O  ONE_BIT  CC1G    :  1; //!<[01] Capture/compare 1 generation
      __O  ONE_BIT  CC2G    :  1; //!<[02] Capture/compare 2 generation
      __O  ONE_BIT  CC3G    :  1; //!<[03] Capture/compare 3 generation
      __O  ONE_BIT  CC4G    :  1; //!<[04] Capture/compare 4 generation
           ONE_BIT  UNUSED0 :  1; //!<[05] 
      __O  ONE_BIT  TG      :  1; //!<[06] Trigger generation
    } B;
    __O  uint32_t  R;
    explicit SWEVGR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      SWEVGR_DEF r;
      R = f (r);
    }
  };
  union CHCTLR1_Input_DEF {  //!< capture/compare mode register 1 (input mode)
    struct {
      __IO uint32_t   CC1S   :  2; //!<[00] Capture/Compare 1 selection
      __IO uint32_t   IC1PSC :  2; //!<[02] Input capture 1 prescaler
      __IO uint32_t   IC1F   :  4; //!<[04] Input capture 1 filter
      __IO uint32_t   CC2S   :  2; //!<[08] Capture/compare 2 selection
      __IO uint32_t   IC2PSC :  2; //!<[10] Input capture 2 prescaler
      __IO uint32_t   IC2F   :  4; //!<[12] Input capture 2 filter
    } B;
    __IO uint32_t  R;
    explicit CHCTLR1_Input_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CHCTLR1_Input_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CHCTLR1_Input_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CHCTLR1_Output_DEF  {  //!< capture/compare mode register 1 (output mode)
    struct {
      __IO uint32_t   CC1S  :  2; //!<[00] Capture/Compare 1 selection
      __IO ONE_BIT    OC1FE :  1; //!<[02] Output compare 1 fast enable
      __IO ONE_BIT    OC1PE :  1; //!<[03] Output compare 1 preload enable
      __IO uint32_t   OC1M  :  3; //!<[04] Output compare 1 mode
      __IO ONE_BIT    OC1CE :  1; //!<[07] Output compare 1 clear enable
      __IO uint32_t   CC2S  :  2; //!<[08] Capture/Compare 2 selection
      __IO ONE_BIT    OC2FE :  1; //!<[10] Output compare 2 fast enable
      __IO ONE_BIT    OC2PE :  1; //!<[11] Output compare 2 preload enable
      __IO uint32_t   OC2M  :  3; //!<[12] Output compare 2 mode
      __IO ONE_BIT    OC2CE :  1; //!<[15] Output compare 2 clear enable
    } B;
    __IO uint32_t  R;
    explicit CHCTLR1_Output_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CHCTLR1_Output_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CHCTLR1_Output_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CHCTLR2_Input_DEF {  //!< capture/compare mode register 2 (input mode)
    struct {
      __IO uint32_t   CC3S   :  2; //!<[00] Capture/Compare 3 selection
      __IO uint32_t   IC3PSC :  2; //!<[02] Input capture 3 prescaler
      __IO uint32_t   IC3F   :  4; //!<[04] Input capture 3 filter
      __IO uint32_t   CC4S   :  2; //!<[08] Capture/Compare 4 selection
      __IO uint32_t   IC4PSC :  2; //!<[10] Input capture 4 prescaler
      __IO uint32_t   IC4F   :  4; //!<[12] Input capture 4 filter
    } B;
    __IO uint32_t  R;
    explicit CHCTLR2_Input_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CHCTLR2_Input_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CHCTLR2_Input_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CHCTLR2_Output_DEF  {  //!< capture/compare mode register 2 (output mode)
    struct {
      __IO uint32_t   CC3S  :  2; //!<[00] Capture/Compare 3 selection
      __IO ONE_BIT    OC3FE :  1; //!<[02] Output compare 3 fast enable
      __IO ONE_BIT    OC3PE :  1; //!<[03] Output compare 3 preload enable
      __IO uint32_t   OC3M  :  3; //!<[04] Output compare 3 mode
      __IO ONE_BIT    OC3CE :  1; //!<[07] Output compare 3 clear enable
      __IO uint32_t   CC4S  :  2; //!<[08] Capture/Compare 4 selection
      __IO ONE_BIT    OC4FE :  1; //!<[10] Output compare 4 fast enable
      __IO ONE_BIT    OC4PE :  1; //!<[11] Output compare 4 preload enable
      __IO uint32_t   OC4M  :  3; //!<[12] Output compare 4 mode
      __IO ONE_BIT    OC4CE :  1; //!<[15] Output compare 4 clear enable
    } B;
    __IO uint32_t  R;
    explicit CHCTLR2_Output_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CHCTLR2_Output_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CHCTLR2_Output_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CCER_DEF          {  //!< capture/compare enable register
    struct {
      __IO ONE_BIT    CC1E    :  1; //!<[00] Capture/Compare 1 output enable
      __IO ONE_BIT    CC1P    :  1; //!<[01] Capture/Compare 1 output Polarity
           uint32_t   UNUSED0 :  2; //!<[02] 
      __IO ONE_BIT    CC2E    :  1; //!<[04] Capture/Compare 2 output enable
      __IO ONE_BIT    CC2P    :  1; //!<[05] Capture/Compare 2 output Polarity
           uint32_t   UNUSED1 :  2; //!<[06] 
      __IO ONE_BIT    CC3E    :  1; //!<[08] Capture/Compare 3 output enable
      __IO ONE_BIT    CC3P    :  1; //!<[09] Capture/Compare 3 output Polarity
           uint32_t   UNUSED2 :  2; //!<[10] 
      __IO ONE_BIT    CC4E    :  1; //!<[12] Capture/Compare 4 output enable
      __IO ONE_BIT    CC4P    :  1; //!<[13] Capture/Compare 3 output Polarity
    } B;
    __IO uint32_t  R;
    explicit CCER_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CCER_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CCER_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CNT_DEF           {  //!< counter
    struct {
      __IO uint32_t   CNT : 16; //!<[00] counter value
    } B;
    __IO uint32_t  R;
    explicit CNT_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CNT_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CNT_DEF r; r.R = R;
      R = f (r);
    }
  };
  union PSC_DEF           {  //!< prescaler
    struct {
      __IO uint32_t   PSC : 16; //!<[00] Prescaler value
    } B;
    __IO uint32_t  R;
    explicit PSC_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      PSC_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      PSC_DEF r; r.R = R;
      R = f (r);
    }
  };
  union ATRLR_DEF         {  //!< auto-reload register
    struct {
      __IO uint32_t   ATRLR : 16; //!<[00] Auto-reload value
    } B;
    __IO uint32_t  R;
    explicit ATRLR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      ATRLR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      ATRLR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CH1CVR_DEF        {  //!< capture/compare register 1
    struct {
      __IO uint32_t   CH1CVR : 16; //!<[00] Capture/Compare 1 value
    } B;
    __IO uint32_t  R;
    explicit CH1CVR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CH1CVR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CH1CVR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CH2CVR_DEF        {  //!< capture/compare register 2
    struct {
      __IO uint32_t   CH2CVR : 16; //!<[00] Capture/Compare 2 value
    } B;
    __IO uint32_t  R;
    explicit CH2CVR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CH2CVR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CH2CVR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CH3CVR_DEF        {  //!< capture/compare register 3
    struct {
      __IO uint32_t   CH3CVR : 16; //!<[00] Capture/Compare value
    } B;
    __IO uint32_t  R;
    explicit CH3CVR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CH3CVR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CH3CVR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CH4CVR_DEF        {  //!< capture/compare register 4
    struct {
      __IO uint32_t   CH4CVR : 16; //!<[00] Capture/Compare value
    } B;
    __IO uint32_t  R;
    explicit CH4CVR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CH4CVR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CH4CVR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union DMACFGR_DEF       {  //!< DMA control register
    struct {
      __IO uint32_t   DBA     :  5; //!<[00] DMA base address
           uint32_t   UNUSED0 :  3; //!<[05] 
      __IO uint32_t   DBL     :  5; //!<[08] DMA burst length
    } B;
    __IO uint32_t  R;
    explicit DMACFGR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      DMACFGR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      DMACFGR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union DMAADR_DEF        {  //!< DMA address for full transfer
    struct {
      __IO uint32_t   DMAADR : 16; //!<[00] DMA register for burst accesses
    } B;
    __IO uint32_t  R;
    explicit DMAADR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      DMAADR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      DMAADR_DEF r; r.R = R;
      R = f (r);
    }
  };
  // PERIPHERAL TIM2 REGISTERS INSTANCES
  __IO CTLR1_DEF                   CTLR1 ;  //!< [0000](04)[0x00000000]
  __IO CTLR2_DEF                   CTLR2 ;  //!< [0004](04)[0x00000000]
  __IO SMCFGR_DEF                 SMCFGR ;  //!< [0008](04)[0x00000000]
  __IO DMAINTENR_DEF           DMAINTENR ;  //!< [000c](04)[0x00000000]
  __IO INTFR_DEF                   INTFR ;  //!< [0010](04)[0x00000000]
  __O  SWEVGR_DEF                 SWEVGR ;  //!< [0014](04)[0x00000000]
  MERGE {
  __IO CHCTLR1_Input_DEF   CHCTLR1_Input ;  //!< [0018](04)[0x00000000]
  __IO CHCTLR1_Output_DEF   CHCTLR1_Output ;  //!< [0018](04)[0x00000000]
  };
  MERGE {
  __IO CHCTLR2_Input_DEF   CHCTLR2_Input ;  //!< [001c](04)[0x00000000]
  __IO CHCTLR2_Output_DEF   CHCTLR2_Output ;  //!< [001c](04)[0x00000000]
  };
  __IO CCER_DEF                     CCER ;  //!< [0020](04)[0x00000000]
  __IO CNT_DEF                       CNT ;  //!< [0024](04)[0x00000000]
  __IO PSC_DEF                       PSC ;  //!< [0028](04)[0x00000000]
  __IO ATRLR_DEF                   ATRLR ;  //!< [002c](04)[0x00000000]
       uint32_t                UNUSED0 ;  //!< [0030](04)[0xFFFFFFFF]
  __IO CH1CVR_DEF                 CH1CVR ;  //!< [0034](04)[0x00000000]
  __IO CH2CVR_DEF                 CH2CVR ;  //!< [0038](04)[0x00000000]
  __IO CH3CVR_DEF                 CH3CVR ;  //!< [003c](04)[0x00000000]
  __IO CH4CVR_DEF                 CH4CVR ;  //!< [0040](04)[0x00000000]
       uint32_t                UNUSED1 ;  //!< [0044](04)[0xFFFFFFFF]
  __IO DMACFGR_DEF               DMACFGR ;  //!< [0048](04)[0x00000000]
  __IO DMAADR_DEF                 DMAADR ;  //!< [004c](04)[0x00000000]
}; /* total size = 0x0400, struct size = 0x0050 */

// ////////////////////+++ I2C1 +-+//////////////////// //
struct I2C1_Type   { /*!< Inter integrated circuit */
  union CTLR1_DEF  {  //!< Control register 1
    struct {
      __IO ONE_BIT    PE        :  1; //!<[00] Peripheral enable
           uint32_t   UNUSED0   :  3; //!<[01] 
      __IO ONE_BIT    ENARP     :  1; //!<[04] ARP enable
      __IO ONE_BIT    ENPEC     :  1; //!<[05] PEC enable
      __IO ONE_BIT    ENGC      :  1; //!<[06] General call enable
      __IO ONE_BIT    NOSTRETCH :  1; //!<[07] Clock stretching disable (Slave mode)
      __IO ONE_BIT    START     :  1; //!<[08] Start generation
      __IO ONE_BIT    STOP      :  1; //!<[09] Stop generation
      __IO ONE_BIT    ACK       :  1; //!<[10] Acknowledge enable
      __IO ONE_BIT    POS       :  1; //!<[11] Acknowledge/PEC Position (for data reception)
      __IO ONE_BIT    PEC       :  1; //!<[12] Packet error checking
           uint32_t   UNUSED1   :  2; //!<[13] 
      __IO ONE_BIT    SWRST     :  1; //!<[15] Software reset
    } B;
    __IO uint32_t  R;
    explicit CTLR1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CTLR1_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CTLR1_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CTLR2_DEF  {  //!< Control register 2
    struct {
      __IO uint32_t   FREQ    :  6; //!<[00] Peripheral clock frequency
           uint32_t   UNUSED0 :  2; //!<[06] 
      __IO ONE_BIT    ITERREN :  1; //!<[08] Error interrupt enable
      __IO ONE_BIT    ITEVTEN :  1; //!<[09] Event interrupt enable
      __IO ONE_BIT    ITBUFEN :  1; //!<[10] Buffer interrupt enable
      __IO ONE_BIT    DMAEN   :  1; //!<[11] DMA requests enable
      __IO ONE_BIT    LAST    :  1; //!<[12] DMA last transfer
    } B;
    __IO uint32_t  R;
    explicit CTLR2_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CTLR2_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CTLR2_DEF r; r.R = R;
      R = f (r);
    }
  };
  union OADDR1_DEF {  //!< Own address register 1
    struct {
      __IO ONE_BIT    ADD0    :  1; //!<[00] Interface address
      __IO uint32_t   ADD7_1  :  7; //!<[01] Interface address
      __IO uint32_t   ADD9_8  :  2; //!<[08] Interface address
           uint32_t   UNUSED0 :  5; //!<[10] 
      __IO ONE_BIT    ADDMODE :  1; //!<[15] Addressing mode (slave mode)
    } B;
    __IO uint32_t  R;
    explicit OADDR1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      OADDR1_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      OADDR1_DEF r; r.R = R;
      R = f (r);
    }
  };
  union OADDR2_DEF {  //!< Own address register 2
    struct {
      __IO ONE_BIT    ENDUAL :  1; //!<[00] Dual addressing mode enable
      __IO uint32_t   ADD2   :  7; //!<[01] Interface address
    } B;
    __IO uint32_t  R;
    explicit OADDR2_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      OADDR2_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      OADDR2_DEF r; r.R = R;
      R = f (r);
    }
  };
  union DATAR_DEF  {  //!< Data register
    struct {
      __IO uint32_t   DATAR :  8; //!<[00] 8-bit data register
    } B;
    __IO uint32_t  R;
    explicit DATAR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      DATAR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      DATAR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union STAR1_DEF  {  //!< Status register 1
    struct {
      __I  ONE_BIT  SB      :  1; //!<[00] Start bit (Master mode)
      __I  ONE_BIT  ADDR    :  1; //!<[01] Address sent (master mode)/matched (slave mode)
      __I  ONE_BIT  BTF     :  1; //!<[02] Byte transfer finished
      __I  ONE_BIT  ADD10   :  1; //!<[03] 10-bit header sent (Master mode)
      __I  ONE_BIT  STOPF   :  1; //!<[04] Stop detection (slave mode)
           ONE_BIT  UNUSED0 :  1; //!<[05] 
      __I  ONE_BIT  RxNE    :  1; //!<[06] Data register not empty (receivers)
      __I  ONE_BIT  TxE     :  1; //!<[07] Data register empty (transmitters)
      __IO ONE_BIT  BERR    :  1; //!<[08] Bus error
      __IO ONE_BIT  ARLO    :  1; //!<[09] Arbitration lost (master mode)
      __IO ONE_BIT  AF      :  1; //!<[10] Acknowledge failure
      __IO ONE_BIT  OVR     :  1; //!<[11] Overrun/Underrun
      __IO ONE_BIT  PECERR  :  1; //!<[12] PEC Error in reception
    } B;
    __IO uint32_t  R;
    explicit STAR1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      STAR1_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      STAR1_DEF r; r.R = R;
      R = f (r);
    }
  };
  union STAR2_DEF  {  //!< Status register 2
    struct {
      __I  ONE_BIT    MSL     :  1; //!<[00] Master/slave
      __I  ONE_BIT    BUSY    :  1; //!<[01] Bus busy
      __I  ONE_BIT    TRA     :  1; //!<[02] Transmitter/receiver
           ONE_BIT    UNUSED0 :  1; //!<[03] 
      __I  ONE_BIT    GENCALL :  1; //!<[04] General call address (Slave mode)
           uint32_t   UNUSED1 :  2; //!<[05] 
      __I  ONE_BIT    DUALF   :  1; //!<[07] Dual flag (Slave mode)
      __I  uint32_t   PEC     :  8; //!<[08] acket error checking register
    } B;
    __I  uint32_t  R;

    explicit STAR2_DEF (volatile STAR2_DEF & o) noexcept { R = o.R; };
  };
  union CKCFGR_DEF {  //!< Clock control register
    struct {
      __IO uint32_t   CCR     : 12; //!<[00] Clock control register in Fast/Standard mode (Master mode)
           uint32_t   UNUSED0 :  2; //!<[12] 
      __IO ONE_BIT    DUTY    :  1; //!<[14] Fast mode duty cycle
      __IO ONE_BIT    F_S     :  1; //!<[15] I2C master mode selection
    } B;
    __IO uint32_t  R;
    explicit CKCFGR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CKCFGR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CKCFGR_DEF r; r.R = R;
      R = f (r);
    }
  };
  // PERIPHERAL I2C1 REGISTERS INSTANCES
  __IO CTLR1_DEF            CTLR1 ;  //!< [0000](04)[0x00000000]
  __IO CTLR2_DEF            CTLR2 ;  //!< [0004](04)[0x00000000]
  __IO OADDR1_DEF          OADDR1 ;  //!< [0008](04)[0x00000000]
  __IO OADDR2_DEF          OADDR2 ;  //!< [000c](04)[0x00000000]
  __IO DATAR_DEF            DATAR ;  //!< [0010](04)[0x00000000]
  __IO STAR1_DEF            STAR1 ;  //!< [0014](04)[0x00000000]
  __I  STAR2_DEF            STAR2 ;  //!< [0018](04)[0x00000000]
  __IO CKCFGR_DEF          CKCFGR ;  //!< [001c](04)[0x00000000]
}; /* total size = 0x0400, struct size = 0x0020 */

// ////////////////////+++ SPI1 +-+//////////////////// //
struct SPI1_Type   { /*!< Serial peripheral interface */
  union CTLR1_DEF   {  //!< control register 1
    struct {
      __IO ONE_BIT    CPHA     :  1; //!<[00] Clock phase
      __IO ONE_BIT    CPOL     :  1; //!<[01] Clock polarity
      __IO ONE_BIT    MSTR     :  1; //!<[02] Master selection
      __IO uint32_t   BR       :  3; //!<[03] Baud rate control
      __IO ONE_BIT    SPE      :  1; //!<[06] SPI enable
      __IO ONE_BIT    LSBFIRST :  1; //!<[07] Frame format
      __IO ONE_BIT    SSI      :  1; //!<[08] Internal slave select
      __IO ONE_BIT    SSM      :  1; //!<[09] Software slave management
      __IO ONE_BIT    RXONLY   :  1; //!<[10] Receive only
      __IO ONE_BIT    DFF      :  1; //!<[11] Data frame format
      __IO ONE_BIT    CRCNEXT  :  1; //!<[12] CRC transfer next
      __IO ONE_BIT    CRCEN    :  1; //!<[13] Hardware CRC calculation enable
      __IO ONE_BIT    BIDIOE   :  1; //!<[14] Output enable in bidirectional mode
      __IO ONE_BIT    BIDIMODE :  1; //!<[15] Bidirectional data mode enable
    } B;
    __IO uint32_t  R;
    explicit CTLR1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CTLR1_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CTLR1_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CTLR2_DEF   {  //!< control register 2
    struct {
      __IO ONE_BIT    RXDMAEN :  1; //!<[00] Rx buffer DMA enable
      __IO ONE_BIT    TXDMAEN :  1; //!<[01] Tx buffer DMA enable
      __IO ONE_BIT    SSOE    :  1; //!<[02] SS output enable
           uint32_t   UNUSED0 :  2; //!<[03] 
      __IO ONE_BIT    ERRIE   :  1; //!<[05] Error interrupt enable
      __IO ONE_BIT    RXNEIE  :  1; //!<[06] RX buffer not empty interrupt enable
      __IO ONE_BIT    TXEIE   :  1; //!<[07] Tx buffer empty interrupt enable
    } B;
    __IO uint32_t  R;
    explicit CTLR2_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CTLR2_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CTLR2_DEF r; r.R = R;
      R = f (r);
    }
  };
  union STATR_DEF   {  //!< status register
    struct {
      __I  ONE_BIT  RXNE   :  1; //!<[00] Receive buffer not empty
      __I  ONE_BIT  TXE    :  1; //!<[01] Transmit buffer empty
      __I  ONE_BIT  CHSID  :  1; //!<[02] Channel side
      __I  ONE_BIT  UDR    :  1; //!<[03] Underrun flag
      __IO ONE_BIT  CRCERR :  1; //!<[04] CRC error flag
      __I  ONE_BIT  MODF   :  1; //!<[05] Mode fault
      __IO ONE_BIT  OVR    :  1; //!<[06] Overrun flag
      __I  ONE_BIT  BSY    :  1; //!<[07] Busy flag
    } B;
    __IO uint32_t  R;
    explicit STATR_DEF () noexcept { R = 0x00000002u; }
    template<typename F> void setbit (F f) volatile {
      STATR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      STATR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union DATAR_DEF   {  //!< data register
    struct {
      __IO uint32_t   DATAR : 16; //!<[00] Data register
    } B;
    __IO uint32_t  R;
    explicit DATAR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      DATAR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      DATAR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CRCR_DEF    {  //!< CRCR polynomial register
    struct {
      __IO uint32_t   CRCPOLY : 16; //!<[00] CRC polynomial register
    } B;
    __IO uint32_t  R;
    explicit CRCR_DEF () noexcept { R = 0x00000007u; }
    template<typename F> void setbit (F f) volatile {
      CRCR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CRCR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union RCRCR_DEF   {  //!< RX CRC register
    struct {
      __I  uint32_t   RXCRC : 16; //!<[00] Rx CRC register
    } B;
    __I  uint32_t  R;

    explicit RCRCR_DEF (volatile RCRCR_DEF & o) noexcept { R = o.R; };
  };
  union TCRCR_DEF   {  //!< send CRC register
    struct {
      __I  uint32_t   TXCRC : 16; //!<[00] Tx CRC register
    } B;
    __I  uint32_t  R;

    explicit TCRCR_DEF (volatile TCRCR_DEF & o) noexcept { R = o.R; };
  };
  union HSCR_DEF    {  //!< high speed control register
    struct {
      __O  ONE_BIT  HSRXEN :  1; //!<[00] High speed mode read enable
    } B;
    __IO uint32_t  R;
    explicit HSCR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      HSCR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      HSCR_DEF r; r.R = R;
      R = f (r);
    }
  };
  // PERIPHERAL SPI1 REGISTERS INSTANCES
  __IO CTLR1_DEF             CTLR1 ;  //!< [0000](04)[0x00000000]
  __IO CTLR2_DEF             CTLR2 ;  //!< [0004](04)[0x00000000]
  __IO STATR_DEF             STATR ;  //!< [0008](04)[0x00000002]
  __IO DATAR_DEF             DATAR ;  //!< [000c](04)[0x00000000]
  __IO CRCR_DEF               CRCR ;  //!< [0010](04)[0x00000007]
  __I  RCRCR_DEF             RCRCR ;  //!< [0014](04)[0x00000000]
  __I  TCRCR_DEF             TCRCR ;  //!< [0018](04)[0x00000000]
       uint32_t          UNUSED0 [2];  //!< [001c](08)[0xFFFFFFFF]
  __IO HSCR_DEF               HSCR ;  //!< [0024](04)[0x00000000]
}; /* total size = 0x0400, struct size = 0x0028 */

// ////////////////////+++ USART1 +-+//////////////////// //
struct USART1_Type { /*!< Universal synchronous asynchronous receiver transmitter */
  union STATR_DEF {  //!< Status register
    struct {
      __I  ONE_BIT  PE   :  1; //!<[00] Parity error
      __I  ONE_BIT  FE   :  1; //!<[01] Framing error
      __I  ONE_BIT  NE   :  1; //!<[02] Noise error flag
      __I  ONE_BIT  ORE  :  1; //!<[03] Overrun error
      __I  ONE_BIT  IDLE :  1; //!<[04] IDLE line detected
      __IO ONE_BIT  RXNE :  1; //!<[05] Read data register not empty
      __IO ONE_BIT  TC   :  1; //!<[06] Transmission complete
      __I  ONE_BIT  TXE  :  1; //!<[07] Transmit data register empty
      __IO ONE_BIT  LBD  :  1; //!<[08] LIN break detection flag
      __IO ONE_BIT  CTS  :  1; //!<[09] CTS flag
    } B;
    __IO uint32_t  R;
    explicit STATR_DEF () noexcept { R = 0x000000c0u; }
    explicit STATR_DEF (volatile STATR_DEF & o) noexcept { R = o.R; };
    template<typename F> void setbit (F f) volatile {
      STATR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      STATR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union DATAR_DEF {  //!< Data register
    struct {
      __IO uint32_t   DR :  9; //!<[00] Data value
    } B;
    __IO uint32_t  R;
    explicit DATAR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      DATAR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      DATAR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union BRR_DEF   {  //!< Baud rate register
    struct {
      __IO uint32_t   DIV_Fraction :  4; //!<[00] fraction of USARTDIV
      __IO uint32_t   DIV_Mantissa : 12; //!<[04] mantissa of USARTDIV
    } B;
    __IO uint32_t  R;
    explicit BRR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      BRR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      BRR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CTLR1_DEF {  //!< Control register 1
    struct {
      __IO ONE_BIT  SBK    :  1; //!<[00] Send break
      __IO ONE_BIT  RWU    :  1; //!<[01] Receiver wakeup
      __IO ONE_BIT  RE     :  1; //!<[02] Receiver enable
      __IO ONE_BIT  TE     :  1; //!<[03] Transmitter enable
      __IO ONE_BIT  IDLEIE :  1; //!<[04] IDLE interrupt enable
      __IO ONE_BIT  RXNEIE :  1; //!<[05] RXNE interrupt enable
      __IO ONE_BIT  TCIE   :  1; //!<[06] Transmission complete interrupt enable
      __IO ONE_BIT  TXEIE  :  1; //!<[07] TXE interrupt enable
      __IO ONE_BIT  PEIE   :  1; //!<[08] PE interrupt enable
      __IO ONE_BIT  PS     :  1; //!<[09] Parity selection
      __IO ONE_BIT  PCE    :  1; //!<[10] Parity control enable
      __IO ONE_BIT  WAKE   :  1; //!<[11] Wakeup method
      __IO ONE_BIT  M      :  1; //!<[12] Word length
      __IO ONE_BIT  UE     :  1; //!<[13] USART enable
    } B;
    __IO uint32_t  R;
    explicit CTLR1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CTLR1_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CTLR1_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CTLR2_DEF {  //!< Control register 2
    struct {
      __IO uint32_t   ADD     :  4; //!<[00] Address of the USART node
           ONE_BIT    UNUSED0 :  1; //!<[04] 
      __IO ONE_BIT    LBDL    :  1; //!<[05] lin break detection length
      __IO ONE_BIT    LBDIE   :  1; //!<[06] LIN break detection interrupt enable
           ONE_BIT    UNUSED1 :  1; //!<[07] 
      __IO ONE_BIT    LBCL    :  1; //!<[08] Last bit clock pulse
      __IO ONE_BIT    CPHA    :  1; //!<[09] Clock phase
      __IO ONE_BIT    CPOL    :  1; //!<[10] Clock polarity
      __IO ONE_BIT    CLKEN   :  1; //!<[11] Clock enable
      __IO uint32_t   STOP    :  2; //!<[12] STOP bits
      __IO ONE_BIT    LINEN   :  1; //!<[14] LIN mode enable
    } B;
    __IO uint32_t  R;
    explicit CTLR2_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CTLR2_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CTLR2_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CTLR3_DEF {  //!< Control register 3
    struct {
      __IO ONE_BIT  EIE   :  1; //!<[00] Error interrupt enable
      __IO ONE_BIT  IREN  :  1; //!<[01] IrDA mode enable
      __IO ONE_BIT  IRLP  :  1; //!<[02] IrDA low-power
      __IO ONE_BIT  HDSEL :  1; //!<[03] Half-duplex selection
      __IO ONE_BIT  NACK  :  1; //!<[04] Smartcard NACK enable
      __IO ONE_BIT  SCEN  :  1; //!<[05] Smartcard mode enable
      __IO ONE_BIT  DMAR  :  1; //!<[06] DMA enable receiver
      __IO ONE_BIT  DMAT  :  1; //!<[07] DMA enable transmitter
      __IO ONE_BIT  RTSE  :  1; //!<[08] RTS enable
      __IO ONE_BIT  CTSE  :  1; //!<[09] CTS enable
      __IO ONE_BIT  CTSIE :  1; //!<[10] CTS interrupt enable
    } B;
    __IO uint32_t  R;
    explicit CTLR3_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CTLR3_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CTLR3_DEF r; r.R = R;
      R = f (r);
    }
  };
  union GPR_DEF   {  //!< Guard time and prescaler register
    struct {
      __IO uint32_t   PSC :  8; //!<[00] Prescaler value
      __IO uint32_t   GT  :  8; //!<[08] Guard time value
    } B;
    __IO uint32_t  R;
    explicit GPR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      GPR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      GPR_DEF r; r.R = R;
      R = f (r);
    }
  };
  // PERIPHERAL USART1 REGISTERS INSTANCES
  __IO STATR_DEF           STATR ;  //!< [0000](04)[0x000000C0]
  __IO DATAR_DEF           DATAR ;  //!< [0004](04)[0x00000000]
  __IO BRR_DEF               BRR ;  //!< [0008](04)[0x00000000]
  __IO CTLR1_DEF           CTLR1 ;  //!< [000c](04)[0x00000000]
  __IO CTLR2_DEF           CTLR2 ;  //!< [0010](04)[0x00000000]
  __IO CTLR3_DEF           CTLR3 ;  //!< [0014](04)[0x00000000]
  __IO GPR_DEF               GPR ;  //!< [0018](04)[0x00000000]
}; /* total size = 0x0400, struct size = 0x001C */

// ////////////////////+++ ADC1 +-+//////////////////// //
struct ADC1_Type   { /*!< Analog to digital converter */
  union STATR_DEF           {  //!< status register
    struct {
      __IO ONE_BIT  AWD   :  1; //!<[00] Analog watchdog flag
      __IO ONE_BIT  EOC   :  1; //!<[01] Regular channel end of conversion
      __IO ONE_BIT  JEOC  :  1; //!<[02] Injected channel end of conversion
      __IO ONE_BIT  JSTRT :  1; //!<[03] Injected channel start flag
      __IO ONE_BIT  STRT  :  1; //!<[04] Regular channel start flag
    } B;
    __IO uint32_t  R;
    explicit STATR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      STATR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      STATR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CTLR1_DEF           {  //!< control register 1/TKEY_V_CTLR
    struct {
      __IO uint32_t   AWDCH       :  5; //!<[00] Analog watchdog channel select bits
      __IO ONE_BIT    EOCIE       :  1; //!<[05] Interrupt enable for EOC
      __IO ONE_BIT    AWDIE       :  1; //!<[06] Analog watchdog interrupt enable
      __IO ONE_BIT    JEOCIE      :  1; //!<[07] Interrupt enable for injected channels
      __IO ONE_BIT    SCAN        :  1; //!<[08] Scan mode enable
      __IO ONE_BIT    AWDSGL      :  1; //!<[09] Enable the watchdog on a single channel in scan mode
      __IO ONE_BIT    JAUTO       :  1; //!<[10] Automatic injected group conversion
      __IO ONE_BIT    DISCEN      :  1; //!<[11] Discontinuous mode on regular channels
      __IO ONE_BIT    JDISCEN     :  1; //!<[12] Discontinuous mode on injected channels
      __IO uint32_t   DISCNUM     :  3; //!<[13] Discontinuous mode channel count
           uint32_t   UNUSED0     :  6; //!<[16] 
      __IO ONE_BIT    JAWDEN      :  1; //!<[22] Analog watchdog enable on injected channels
      __IO ONE_BIT    AWDEN       :  1; //!<[23] Analog watchdog enable on regular channels
           ONE_BIT    UNUSED1     :  1; //!<[24] 
      __IO uint32_t   ADC_CAL_VOL :  2; //!<[25] ADC Calibration voltage selection
    } B;
    __IO uint32_t  R;
    explicit CTLR1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CTLR1_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CTLR1_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CTLR2_DEF           {  //!< control register 2
    struct {
      __IO ONE_BIT    ADON     :  1; //!<[00] A/D converter ON / OFF
      __IO ONE_BIT    CONT     :  1; //!<[01] Continuous conversion
      __IO ONE_BIT    CAL      :  1; //!<[02] A/D calibration
      __IO ONE_BIT    RSTCAL   :  1; //!<[03] Reset calibration
           uint32_t   UNUSED0  :  4; //!<[04] 
      __IO ONE_BIT    DMA      :  1; //!<[08] Direct memory access mode
           uint32_t   UNUSED1  :  2; //!<[09] 
      __IO ONE_BIT    ALIGN    :  1; //!<[11] Data alignment
      __IO uint32_t   JEXTSEL  :  3; //!<[12] External event select for injected group
      __IO ONE_BIT    JEXTTRIG :  1; //!<[15] External trigger conversion mode for injected channels
           ONE_BIT    UNUSED2  :  1; //!<[16] 
      __IO uint32_t   EXTSEL   :  3; //!<[17] External event select for regular group
      __IO ONE_BIT    EXTTRIG  :  1; //!<[20] External trigger conversion mode for regular channels
      __IO ONE_BIT    JSWSTART :  1; //!<[21] Start conversion of injected channels
      __IO ONE_BIT    SWSTART  :  1; //!<[22] Start conversion of regular channels
    } B;
    __IO uint32_t  R;
    explicit CTLR2_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CTLR2_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CTLR2_DEF r; r.R = R;
      R = f (r);
    }
  };
  union SAMPTR1_CHARGE1_DEF {  //!< sample time register 1
    struct {
      __IO uint32_t   SMP10_TKCG10 :  3; //!<[00] Channel 10 sample time selection
      __IO uint32_t   SMP11_TKCG11 :  3; //!<[03] Channel 11 sample time selection
      __IO uint32_t   SMP12_TKCG12 :  3; //!<[06] Channel 12 sample time selection
      __IO uint32_t   SMP13_TKCG13 :  3; //!<[09] Channel 13 sample time selection
      __IO uint32_t   SMP14_TKCG14 :  3; //!<[12] Channel 14 sample time selection
      __IO uint32_t   SMP15_TKCG15 :  3; //!<[15] Channel 15 sample time selection
    } B;
    __IO uint32_t  R;
    explicit SAMPTR1_CHARGE1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      SAMPTR1_CHARGE1_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      SAMPTR1_CHARGE1_DEF r; r.R = R;
      R = f (r);
    }
  };
  union SAMPTR2_CHARGE2_DEF {  //!< sample time register 2
    struct {
      __IO uint32_t   SMP0_TKCG0 :  3; //!<[00] Channel 0 sample time selection
      __IO uint32_t   SMP1_TKCG1 :  3; //!<[03] Channel 1 sample time selection
      __IO uint32_t   SMP2_TKCG2 :  3; //!<[06] Channel 2 sample time selection
      __IO uint32_t   SMP3_TKCG3 :  3; //!<[09] Channel 3 sample time selection
      __IO uint32_t   SMP4_TKCG4 :  3; //!<[12] Channel 4 sample time selection
      __IO uint32_t   SMP5_TKCG5 :  3; //!<[15] Channel 5 sample time selection
      __IO uint32_t   SMP6_TKCG6 :  3; //!<[18] Channel 6 sample time selection
      __IO uint32_t   SMP7_TKCG7 :  3; //!<[21] Channel 7 sample time selection
      __IO uint32_t   SMP8_TKCG8 :  3; //!<[24] Channel 8 sample time selection
      __IO uint32_t   SMP9_TKCG9 :  3; //!<[27] Channel 9 sample time selection
    } B;
    __IO uint32_t  R;
    explicit SAMPTR2_CHARGE2_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      SAMPTR2_CHARGE2_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      SAMPTR2_CHARGE2_DEF r; r.R = R;
      R = f (r);
    }
  };
  union IOFR1_DEF           {  //!< injected channel data offset register x
    struct {
      __IO uint32_t   JOFFSET1 : 10; //!<[00] Data offset for injected channel x
    } B;
    __IO uint32_t  R;
    explicit IOFR1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IOFR1_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      IOFR1_DEF r; r.R = R;
      R = f (r);
    }
  };
  union IOFR2_DEF           {  //!< injected channel data offset register x
    struct {
      __IO uint32_t   JOFFSET2 : 10; //!<[00] Data offset for injected channel x
    } B;
    __IO uint32_t  R;
    explicit IOFR2_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IOFR2_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      IOFR2_DEF r; r.R = R;
      R = f (r);
    }
  };
  union IOFR3_DEF           {  //!< injected channel data offset register x
    struct {
      __IO uint32_t   JOFFSET3 : 10; //!<[00] Data offset for injected channel x
    } B;
    __IO uint32_t  R;
    explicit IOFR3_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IOFR3_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      IOFR3_DEF r; r.R = R;
      R = f (r);
    }
  };
  union IOFR4_DEF           {  //!< injected channel data offset register x
    struct {
      __IO uint32_t   JOFFSET4 : 10; //!<[00] Data offset for injected channel x
    } B;
    __IO uint32_t  R;
    explicit IOFR4_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IOFR4_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      IOFR4_DEF r; r.R = R;
      R = f (r);
    }
  };
  union WDHTR_DEF           {  //!< watchdog higher threshold register
    struct {
      __IO uint32_t   HT : 10; //!<[00] Analog watchdog higher threshold
    } B;
    __IO uint32_t  R;
    explicit WDHTR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      WDHTR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      WDHTR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union WDLTR_DEF           {  //!< watchdog lower threshold register
    struct {
      __IO uint32_t   LT : 10; //!<[00] Analog watchdog lower threshold
    } B;
    __IO uint32_t  R;
    explicit WDLTR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      WDLTR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      WDLTR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union RSQR1_DEF           {  //!< regular sequence register 1
    struct {
      __IO uint32_t   SQ13 :  5; //!<[00] 13th conversion in regular sequence
      __IO uint32_t   SQ14 :  5; //!<[05] 14th conversion in regular sequence
      __IO uint32_t   SQ15 :  5; //!<[10] 15th conversion in regular sequence
      __IO uint32_t   SQ16 :  5; //!<[15] 16th conversion in regular sequence
      __IO uint32_t   L    :  4; //!<[20] Regular channel sequence length
    } B;
    __IO uint32_t  R;
    explicit RSQR1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      RSQR1_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      RSQR1_DEF r; r.R = R;
      R = f (r);
    }
  };
  union RSQR2_DEF           {  //!< regular sequence register 2
    struct {
      __IO uint32_t   SQ7  :  5; //!<[00] 7th conversion in regular sequence
      __IO uint32_t   SQ8  :  5; //!<[05] 8th conversion in regular sequence
      __IO uint32_t   SQ9  :  5; //!<[10] 9th conversion in regular sequence
      __IO uint32_t   SQ10 :  5; //!<[15] 10th conversion in regular sequence
      __IO uint32_t   SQ11 :  5; //!<[20] 11th conversion in regular sequence
      __IO uint32_t   SQ12 :  5; //!<[25] 12th conversion in regular sequence
    } B;
    __IO uint32_t  R;
    explicit RSQR2_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      RSQR2_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      RSQR2_DEF r; r.R = R;
      R = f (r);
    }
  };
  union RSQR3_DEF           {  //!< regular sequence register 3
    struct {
      __IO uint32_t   SQ1 :  5; //!<[00] 1st conversion in regular sequence
      __IO uint32_t   SQ2 :  5; //!<[05] 2nd conversion in regular sequence
      __IO uint32_t   SQ3 :  5; //!<[10] 3rd conversion in regular sequence
      __IO uint32_t   SQ4 :  5; //!<[15] 4th conversion in regular sequence
      __IO uint32_t   SQ5 :  5; //!<[20] 5th conversion in regular sequence
      __IO uint32_t   SQ6 :  5; //!<[25] 6th conversion in regular sequence
    } B;
    __IO uint32_t  R;
    explicit RSQR3_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      RSQR3_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      RSQR3_DEF r; r.R = R;
      R = f (r);
    }
  };
  union ISQR_DEF            {  //!< injected sequence register
    struct {
      __IO uint32_t   JSQ1 :  5; //!<[00] 1st conversion in injected sequence
      __IO uint32_t   JSQ2 :  5; //!<[05] 2nd conversion in injected sequence
      __IO uint32_t   JSQ3 :  5; //!<[10] 3rd conversion in injected sequence
      __IO uint32_t   JSQ4 :  5; //!<[15] 4th conversion in injected sequence
      __IO uint32_t   JL   :  2; //!<[20] Injected sequence length
    } B;
    __IO uint32_t  R;
    explicit ISQR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      ISQR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      ISQR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union IDATAR1_DEF         {  //!< injected data register 1
    struct {
      __I  uint32_t   IDATA : 16; //!<[00] Injected data
    } B;
    __I  uint32_t  R;

    explicit IDATAR1_DEF (volatile IDATAR1_DEF & o) noexcept { R = o.R; };
  };
  union IDATAR2_DEF         {  //!< injected data register 2
    struct {
      __I  uint32_t   IDATA : 16; //!<[00] Injected data
    } B;
    __I  uint32_t  R;

    explicit IDATAR2_DEF (volatile IDATAR2_DEF & o) noexcept { R = o.R; };
  };
  union IDATAR3_DEF         {  //!< injected data register 3
    struct {
      __I  uint32_t   IDATA : 16; //!<[00] Injected data
    } B;
    __I  uint32_t  R;

    explicit IDATAR3_DEF (volatile IDATAR3_DEF & o) noexcept { R = o.R; };
  };
  union IDATAR4_DEF         {  //!< injected data register 4
    struct {
      __I  uint32_t   IDATA : 16; //!<[00] Injected data
    } B;
    __I  uint32_t  R;

    explicit IDATAR4_DEF (volatile IDATAR4_DEF & o) noexcept { R = o.R; };
  };
  union RDATAR_DEF          {  //!< regular data register
    struct {
      __I  uint32_t   DATA : 32; //!<[00] Regular data
    } B;
    __I  uint32_t  R;

    explicit RDATAR_DEF (volatile RDATAR_DEF & o) noexcept { R = o.R; };
  };
  union DLYR_DEF            {  //!< delay data register
    struct {
      __IO uint32_t   DLYVLU :  9; //!<[00] External trigger data delay time configuration
      __IO ONE_BIT    DLYSRC :  1; //!<[09] External trigger source delay selection
    } B;
    __IO uint32_t  R;
    explicit DLYR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      DLYR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      DLYR_DEF r; r.R = R;
      R = f (r);
    }
  };
  // PERIPHERAL ADC1 REGISTERS INSTANCES
  __IO STATR_DEF                     STATR ;  //!< [0000](04)[0x00000000]
  __IO CTLR1_DEF                     CTLR1 ;  //!< [0004](04)[0x00000000]
  __IO CTLR2_DEF                     CTLR2 ;  //!< [0008](04)[0x00000000]
  __IO SAMPTR1_CHARGE1_DEF SAMPTR1_CHARGE1 ;  //!< [000c](04)[0x00000000]
  __IO SAMPTR2_CHARGE2_DEF SAMPTR2_CHARGE2 ;  //!< [0010](04)[0x00000000]
  __IO IOFR1_DEF                     IOFR1 ;  //!< [0014](04)[0x00000000]
  __IO IOFR2_DEF                     IOFR2 ;  //!< [0018](04)[0x00000000]
  __IO IOFR3_DEF                     IOFR3 ;  //!< [001c](04)[0x00000000]
  __IO IOFR4_DEF                     IOFR4 ;  //!< [0020](04)[0x00000000]
  __IO WDHTR_DEF                     WDHTR ;  //!< [0024](04)[0x00000000]
  __IO WDLTR_DEF                     WDLTR ;  //!< [0028](04)[0x00000000]
  __IO RSQR1_DEF                     RSQR1 ;  //!< [002c](04)[0x00000000]
  __IO RSQR2_DEF                     RSQR2 ;  //!< [0030](04)[0x00000000]
  __IO RSQR3_DEF                     RSQR3 ;  //!< [0034](04)[0x00000000]
  __IO ISQR_DEF                       ISQR ;  //!< [0038](04)[0x00000000]
  __I  IDATAR1_DEF                 IDATAR1 ;  //!< [003c](04)[0x00000000]
  __I  IDATAR2_DEF                 IDATAR2 ;  //!< [0040](04)[0x00000000]
  __I  IDATAR3_DEF                 IDATAR3 ;  //!< [0044](04)[0x00000000]
  __I  IDATAR4_DEF                 IDATAR4 ;  //!< [0048](04)[0x00000000]
  __I  RDATAR_DEF                   RDATAR ;  //!< [004c](04)[0x00000000]
  __IO DLYR_DEF                       DLYR ;  //!< [0050](04)[0x00000000]
}; /* total size = 0x0400, struct size = 0x0054 */

// ////////////////////+++ DBG +-+//////////////////// //
struct DBG_Type    { /*!< Debug support */
  union CFGR1_DEF {  //!< DBGMCU_CFGR1
    struct {
      __IO ONE_BIT  DEG_IWDG :  1; //!<[00] DEG_IWDG
      __IO ONE_BIT  DEG_WWDG :  1; //!<[01] DEG_WWDG
      __IO ONE_BIT  DEG_I2C1 :  1; //!<[02] DEG_I2C1
           ONE_BIT  UNUSED0  :  1; //!<[03] 
      __IO ONE_BIT  DEG_TIM1 :  1; //!<[04] DEG_TIM1
      __IO ONE_BIT  DEG_TIM2 :  1; //!<[05] DEG_TIM2
    } B;
    __IO uint32_t  R;
    explicit CFGR1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CFGR1_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CFGR1_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CFGR2_DEF {  //!< DBGMCU_CFGR2
    struct {
      __IO ONE_BIT  DBG_SLEEP   :  1; //!<[00] DBG_SLEEP
      __IO ONE_BIT  DBG_STOP    :  1; //!<[01] DBG_STOP
      __IO ONE_BIT  DBG_STANDBY :  1; //!<[02] DBG_STANDBY
    } B;
    __IO uint32_t  R;
    explicit CFGR2_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CFGR2_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CFGR2_DEF r; r.R = R;
      R = f (r);
    }
  };
  // PERIPHERAL DBG REGISTERS INSTANCES
  __IO CFGR1_DEF           CFGR1 ;  //!< [0000](04)[0x00000000]
  __IO CFGR2_DEF           CFGR2 ;  //!< [0004](04)[0x00000000]
}; /* total size = 0x0400, struct size = 0x0008 */

// ////////////////////+++ ESIG +-+//////////////////// //
struct ESIG_Type   { /*!< Device electronic signature */
  union FLACAP_DEF  {  //!< Flash capacity register
    struct {
      __I  uint16_t   FLASHSIZE : 16; //!<[00] Flash size
    } B;
    __I  uint16_t  R;
  };
  union UNIID1_DEF  {  //!< Unique identity 1
    struct {
      __I  uint32_t   U_ID : 32; //!<[00] Unique identity[31:0]
    } B;
    __I  uint32_t  R;

    explicit UNIID1_DEF (volatile UNIID1_DEF & o) noexcept { R = o.R; };
  };
  union UNIID2_DEF  {  //!< Unique identity 2
    struct {
      __I  uint32_t   U_ID : 32; //!<[00] Unique identity[63:32]
    } B;
    __I  uint32_t  R;

    explicit UNIID2_DEF (volatile UNIID2_DEF & o) noexcept { R = o.R; };
  };
  union UNIID3_DEF  {  //!< Unique identity 3
    struct {
      __I  uint32_t   U_ID : 32; //!<[00] Unique identity[95:64]
    } B;
    __I  uint32_t  R;

    explicit UNIID3_DEF (volatile UNIID3_DEF & o) noexcept { R = o.R; };
  };
  // PERIPHERAL ESIG REGISTERS INSTANCES
  __I  FLACAP_DEF           FLACAP ;  //!< [0000](02)[0x00000000]
       uint8_t           UNUSED0 [6];  //!< [0002](06)[0xFFFFFFFF]
  __I  UNIID1_DEF           UNIID1 ;  //!< [0008](04)[0x00000000]
  __I  UNIID2_DEF           UNIID2 ;  //!< [000c](04)[0x00000000]
  __I  UNIID3_DEF           UNIID3 ;  //!< [0010](04)[0x00000000]
}; /* total size = 0x0014, struct size = 0x0014 */

// ////////////////////+++ FLASH +-+//////////////////// //
struct FLASH_Type  { /*!< FLASH */
  union ACTLR_DEF         {  //!< Flash key register
    struct {
      __IO ONE_BIT  LATENCY :  1; //!<[00] Number of FLASH wait states
    } B;
    __IO uint32_t  R;
    explicit ACTLR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      ACTLR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      ACTLR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union KEYR_DEF          {  //!< Flash key register
    struct {
      __O  uint32_t   KEYR : 32; //!<[00] FPEC key
    } B;
    __O  uint32_t  R;
    explicit KEYR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      KEYR_DEF r;
      R = f (r);
    }
  };
  union OBKEYR_DEF        {  //!< Flash option key register
    struct {
      __O  uint32_t   OPTKEY : 32; //!<[00] Option byte key
    } B;
    __O  uint32_t  R;
    explicit OBKEYR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      OBKEYR_DEF r;
      R = f (r);
    }
  };
  union STATR_DEF         {  //!< Status register
    struct {
      __I  ONE_BIT    BSY       :  1; //!<[00] Busy
           uint32_t   UNUSED0   :  3; //!<[01] 
      __IO ONE_BIT    WRPRTERR  :  1; //!<[04] Write protection error
      __IO ONE_BIT    EOP       :  1; //!<[05] End of operation
           uint32_t   UNUSED1   :  8; //!<[06] 
      __IO ONE_BIT    BOOT_MODE :  1; //!<[14] BOOT mode
      __IO ONE_BIT    BOOT_LOCK :  1; //!<[15] BOOT lock
    } B;
    __IO uint32_t  R;
    explicit STATR_DEF () noexcept { R = 0x00008000u; }
    template<typename F> void setbit (F f) volatile {
      STATR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      STATR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CTLR_DEF          {  //!< Control register
    struct {
      __IO ONE_BIT    PG      :  1; //!<[00] Programming
      __IO ONE_BIT    PER     :  1; //!<[01] Page Erase
      __IO ONE_BIT    MER     :  1; //!<[02] Mass Erase
           ONE_BIT    UNUSED0 :  1; //!<[03] 
      __IO ONE_BIT    OBPG    :  1; //!<[04] Option byte programming
      __IO ONE_BIT    OBER    :  1; //!<[05] Option byte erase
      __IO ONE_BIT    STRT    :  1; //!<[06] Start
      __IO ONE_BIT    LOCK    :  1; //!<[07] Lock
           ONE_BIT    UNUSED1 :  1; //!<[08] 
      __IO ONE_BIT    OBWRE   :  1; //!<[09] Option bytes write enable
      __IO ONE_BIT    ERRIE   :  1; //!<[10] Error interrupt enable
           ONE_BIT    UNUSED2 :  1; //!<[11] 
      __IO ONE_BIT    EOPIE   :  1; //!<[12] End of operation interrupt enable
           uint32_t   UNUSED3 :  2; //!<[13] 
      __IO ONE_BIT    FLOCK   :  1; //!<[15] Fast programmable lock
      __IO ONE_BIT    PAGE_PG :  1; //!<[16] Fast programming
      __IO ONE_BIT    PAGE_ER :  1; //!<[17] Fast erase
      __IO ONE_BIT    BUFLOAD :  1; //!<[18] Buffer load
      __IO ONE_BIT    BUFRST  :  1; //!<[19] Buffer reset
    } B;
    __IO uint32_t  R;
    explicit CTLR_DEF () noexcept { R = 0x00008080u; }
    template<typename F> void setbit (F f) volatile {
      CTLR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CTLR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union ADDR_DEF          {  //!< Flash address register
    struct {
      __O  uint32_t   ADDR : 32; //!<[00] Flash Address
    } B;
    __O  uint32_t  R;
    explicit ADDR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      ADDR_DEF r;
      R = f (r);
    }
  };
  union OBR_DEF           {  //!< Option byte register
    struct {
      __I  ONE_BIT    OBERR        :  1; //!<[00] Option byte error
      __I  ONE_BIT    RDPRT        :  1; //!<[01] Read protection
      __I  ONE_BIT    IWDG_SW      :  1; //!<[02] IWDG_SW
      __I  ONE_BIT    STOP_RST     :  1; //!<[03] STOP_RST
      __I  ONE_BIT    STANDY_RST   :  1; //!<[04] STANDY_RST
      __I  uint32_t   CFG_RST_MODE :  2; //!<[05] CFG_RST_MODE
           uint32_t   UNUSED0      :  3; //!<[07] 
      __I  uint32_t   DATA0        :  8; //!<[10] DATA0
      __I  uint32_t   DATA1        :  8; //!<[18] DATA1
    } B;
    __I  uint32_t  R;

    explicit OBR_DEF (volatile OBR_DEF & o) noexcept { R = o.R; };
  };
  union WPR_DEF           {  //!< Write protection register
    struct {
      __I  uint32_t   WRP : 32; //!<[00] Write protect
    } B;
    __I  uint32_t  R;

    explicit WPR_DEF (volatile WPR_DEF & o) noexcept { R = o.R; };
  };
  union MODEKEYR_DEF      {  //!< Mode select register
    struct {
      __O  uint32_t   MODEKEYR : 32; //!<[00] Mode select
    } B;
    __O  uint32_t  R;
    explicit MODEKEYR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      MODEKEYR_DEF r;
      R = f (r);
    }
  };
  union BOOT_MODEKEYP_DEF {  //!< Boot mode key register
    struct {
      __O  uint32_t   MODEKEYR : 32; //!<[00] Boot mode key
    } B;
    __O  uint32_t  R;
    explicit BOOT_MODEKEYP_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      BOOT_MODEKEYP_DEF r;
      R = f (r);
    }
  };
  // PERIPHERAL FLASH REGISTERS INSTANCES
  __IO ACTLR_DEF                   ACTLR ;  //!< [0000](04)[0x00000000]
  __O  KEYR_DEF                     KEYR ;  //!< [0004](04)[0x00000000]
  __O  OBKEYR_DEF                 OBKEYR ;  //!< [0008](04)[0x00000000]
  __IO STATR_DEF                   STATR ;  //!< [000c](04)[0x00008000]
  __IO CTLR_DEF                     CTLR ;  //!< [0010](04)[0x00008080]
  __O  ADDR_DEF                     ADDR ;  //!< [0014](04)[0x00000000]
       uint32_t                UNUSED0 ;  //!< [0018](04)[0xFFFFFFFF]
  __I  OBR_DEF                       OBR ;  //!< [001c](04)[0x03FFFFFE]
  __I  WPR_DEF                       WPR ;  //!< [0020](04)[0xFFFFFFFF]
  __O  MODEKEYR_DEF             MODEKEYR ;  //!< [0024](04)[0x00000000]
  __O  BOOT_MODEKEYP_DEF   BOOT_MODEKEYP ;  //!< [0028](04)[0x00000000]
}; /* total size = 0x0400, struct size = 0x002C */

// ////////////////////+++ PFIC +-+//////////////////// //
struct PFIC_Type   { /*!< Programmable Fast Interrupt Controller */
  union ISR1_DEF      {  //!< Interrupt Status Register
    struct {
           uint32_t   UNUSED0       :  2; //!<[00] 
      __I  uint32_t   INTENSTA2_3   :  2; //!<[02] Interrupt ID Status
           uint32_t   UNUSED1       :  8; //!<[04] 
      __I  uint32_t   INTENSTA12_31 : 20; //!<[12] Interrupt ID Status
    } B;
    __I  uint32_t  R;

    explicit ISR1_DEF (volatile ISR1_DEF & o) noexcept { R = o.R; };
  };
  union ISR2_DEF      {  //!< Interrupt Status Register
    struct {
      __I  uint32_t   INTENSTA : 32; //!<[00] Interrupt ID Status
    } B;
    __I  uint32_t  R;

    explicit ISR2_DEF (volatile ISR2_DEF & o) noexcept { R = o.R; };
  };
  union ISR3_DEF      {  //!< Interrupt Status Register
    struct {
      __I  uint32_t   INTENSTA : 32; //!<[00] Interrupt ID Status
    } B;
    __I  uint32_t  R;

    explicit ISR3_DEF (volatile ISR3_DEF & o) noexcept { R = o.R; };
  };
  union ISR4_DEF      {  //!< Interrupt Status Register
    struct {
      __I  uint32_t   INTENSTA :  8; //!<[00] Interrupt ID Status
    } B;
    __I  uint32_t  R;

    explicit ISR4_DEF (volatile ISR4_DEF & o) noexcept { R = o.R; };
  };
  union IPR1_DEF      {  //!< Interrupt Pending Register
    struct {
           uint32_t   UNUSED0      :  2; //!<[00] 
      __I  uint32_t   PENDSTA2_3   :  2; //!<[02] PENDSTA
           uint32_t   UNUSED1      :  8; //!<[04] 
      __I  uint32_t   PENDSTA12_31 : 20; //!<[12] PENDSTA
    } B;
    __I  uint32_t  R;

    explicit IPR1_DEF (volatile IPR1_DEF & o) noexcept { R = o.R; };
  };
  union IPR2_DEF      {  //!< Interrupt Pending Register
    struct {
      __I  uint32_t   PENDSTA : 32; //!<[00] PENDSTA
    } B;
    __I  uint32_t  R;

    explicit IPR2_DEF (volatile IPR2_DEF & o) noexcept { R = o.R; };
  };
  union IPR3_DEF      {  //!< Interrupt Pending Register
    struct {
      __I  uint32_t   PENDSTA : 32; //!<[00] PENDSTA
    } B;
    __I  uint32_t  R;

    explicit IPR3_DEF (volatile IPR3_DEF & o) noexcept { R = o.R; };
  };
  union IPR4_DEF      {  //!< Interrupt Pending Register
    struct {
      __I  uint32_t   PENDSTA :  8; //!<[00] PENDSTA
    } B;
    __I  uint32_t  R;

    explicit IPR4_DEF (volatile IPR4_DEF & o) noexcept { R = o.R; };
  };
  union ITHRESDR_DEF  {  //!< Interrupt Priority Register
    struct {
      __IO uint32_t   THRESHOLD :  8; //!<[00] THRESHOLD
    } B;
    __IO uint32_t  R;
    explicit ITHRESDR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      ITHRESDR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      ITHRESDR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union CFGR_DEF      {  //!< Interrupt Config Register
    struct {
           uint32_t   UNUSED0  :  7; //!<[00] 
      __O  ONE_BIT    RESETSYS :  1; //!<[07] RESETSYS
           uint32_t   UNUSED1  :  8; //!<[08] 
      __O  uint32_t   KEYCODE  : 16; //!<[16] KEYCODE
    } B;
    __IO uint32_t  R;
    explicit CFGR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      CFGR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      CFGR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union GISR_DEF      {  //!< Interrupt Global Register
    struct {
      __I  uint32_t   NESTSTA  :  8; //!<[00] NESTSTA
      __I  ONE_BIT    GACTSTA  :  1; //!<[08] GACTSTA
      __I  ONE_BIT    GPENDSTA :  1; //!<[09] GPENDSTA
    } B;
    __I  uint32_t  R;

    explicit GISR_DEF (volatile GISR_DEF & o) noexcept { R = o.R; };
  };
  union VTFIDR_DEF    {  //!< ID Config Register
    struct {
      __IO uint32_t   VTFID0 :  8; //!<[00] VTFID0
      __IO uint32_t   VTFID1 :  8; //!<[08] VTFID1
      __IO uint32_t   VTFID2 :  8; //!<[16] VTFID2
      __IO uint32_t   VTFID3 :  8; //!<[24] VTFID3
    } B;
    __IO uint32_t  R;
    explicit VTFIDR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      VTFIDR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      VTFIDR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union VTFADDRR0_DEF {  //!< Interrupt 0 address Register
    struct {
      __IO ONE_BIT    VTF0EN :  1; //!<[00] VTF0EN
      __IO uint32_t    ADDR0 : 31; //!<[01]  ADDR0
    } B;
    __IO uint32_t  R;
    explicit VTFADDRR0_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      VTFADDRR0_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      VTFADDRR0_DEF r; r.R = R;
      R = f (r);
    }
  };
  union VTFADDRR1_DEF {  //!< Interrupt 1 address Register
    struct {
      __IO ONE_BIT    VTF1EN :  1; //!<[00] VTF1EN
      __IO uint32_t    ADDR1 : 31; //!<[01]  ADDR1
    } B;
    __IO uint32_t  R;
    explicit VTFADDRR1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      VTFADDRR1_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      VTFADDRR1_DEF r; r.R = R;
      R = f (r);
    }
  };
  union VTFADDRR2_DEF {  //!< Interrupt 2 address Register
    struct {
      __IO ONE_BIT    VTF2EN :  1; //!<[00] VTF2EN
      __IO uint32_t    ADDR2 : 31; //!<[01]  ADDR2
    } B;
    __IO uint32_t  R;
    explicit VTFADDRR2_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      VTFADDRR2_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      VTFADDRR2_DEF r; r.R = R;
      R = f (r);
    }
  };
  union VTFADDRR3_DEF {  //!< Interrupt 3 address Register
    struct {
      __IO ONE_BIT    VTF3EN :  1; //!<[00] VTF3EN
      __IO uint32_t    ADDR3 : 31; //!<[01]  ADDR3
    } B;
    __IO uint32_t  R;
    explicit VTFADDRR3_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      VTFADDRR3_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      VTFADDRR3_DEF r; r.R = R;
      R = f (r);
    }
  };
  union IENR1_DEF     {  //!< Interrupt Setting Register
    struct {
           uint32_t   UNUSED0 : 12; //!<[00] 
      __O  uint32_t   INTEN   : 20; //!<[12] INTEN
    } B;
    __O  uint32_t  R;
    explicit IENR1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IENR1_DEF r;
      R = f (r);
    }
  };
  union IENR2_DEF     {  //!< Interrupt Setting Register
    struct {
      __O  uint32_t   INTEN : 32; //!<[00] INTEN
    } B;
    __O  uint32_t  R;
    explicit IENR2_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IENR2_DEF r;
      R = f (r);
    }
  };
  union IENR3_DEF     {  //!< Interrupt Setting Register
    struct {
      __O  uint32_t   INTEN : 32; //!<[00] INTEN
    } B;
    __O  uint32_t  R;
    explicit IENR3_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IENR3_DEF r;
      R = f (r);
    }
  };
  union IENR4_DEF     {  //!< Interrupt Setting Register
    struct {
      __O  uint32_t   INTEN :  8; //!<[00] INTEN
    } B;
    __O  uint32_t  R;
    explicit IENR4_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IENR4_DEF r;
      R = f (r);
    }
  };
  union IRER1_DEF     {  //!< Interrupt Clear Register
    struct {
           uint32_t   UNUSED0 : 12; //!<[00] 
      __O  uint32_t   INTRSET : 20; //!<[12] INTRSET
    } B;
    __O  uint32_t  R;
    explicit IRER1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IRER1_DEF r;
      R = f (r);
    }
  };
  union IRER2_DEF     {  //!< Interrupt Clear Register
    struct {
      __O  uint32_t   INTRSET : 32; //!<[00] INTRSET
    } B;
    __O  uint32_t  R;
    explicit IRER2_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IRER2_DEF r;
      R = f (r);
    }
  };
  union IRER3_DEF     {  //!< Interrupt Clear Register
    struct {
      __O  uint32_t   INTRSET : 32; //!<[00] INTRSET
    } B;
    __O  uint32_t  R;
    explicit IRER3_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IRER3_DEF r;
      R = f (r);
    }
  };
  union IRER4_DEF     {  //!< Interrupt Clear Register
    struct {
      __O  uint32_t   INTRSET :  8; //!<[00] INTRSET
    } B;
    __O  uint32_t  R;
    explicit IRER4_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IRER4_DEF r;
      R = f (r);
    }
  };
  union IPSR1_DEF     {  //!< Interrupt Pending Register
    struct {
           uint32_t   UNUSED0      :  2; //!<[00] 
      __O  uint32_t   PENDSET2_3   :  2; //!<[02] PENDSET
           uint32_t   UNUSED1      :  8; //!<[04] 
      __O  uint32_t   PENDSET12_31 : 20; //!<[12] PENDSET
    } B;
    __O  uint32_t  R;
    explicit IPSR1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IPSR1_DEF r;
      R = f (r);
    }
  };
  union IPSR2_DEF     {  //!< Interrupt Pending Register
    struct {
      __O  uint32_t   PENDSET : 32; //!<[00] PENDSET
    } B;
    __O  uint32_t  R;
    explicit IPSR2_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IPSR2_DEF r;
      R = f (r);
    }
  };
  union IPSR3_DEF     {  //!< Interrupt Pending Register
    struct {
      __O  uint32_t   PENDSET : 32; //!<[00] PENDSET
    } B;
    __O  uint32_t  R;
    explicit IPSR3_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IPSR3_DEF r;
      R = f (r);
    }
  };
  union IPSR4_DEF     {  //!< Interrupt Pending Register
    struct {
      __O  uint32_t   PENDSET :  8; //!<[00] PENDSET
    } B;
    __O  uint32_t  R;
    explicit IPSR4_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IPSR4_DEF r;
      R = f (r);
    }
  };
  union IPRR1_DEF     {  //!< Interrupt Pending Clear Register
    struct {
           uint32_t   UNUSED0        :  2; //!<[00] 
      __O  uint32_t   PENDRESET2_3   :  2; //!<[02] PENDRESET
           uint32_t   UNUSED1        :  8; //!<[04] 
      __O  uint32_t   PENDRESET12_31 : 20; //!<[12] PENDRESET
    } B;
    __O  uint32_t  R;
    explicit IPRR1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IPRR1_DEF r;
      R = f (r);
    }
  };
  union IPRR2_DEF     {  //!< Interrupt Pending Clear Register
    struct {
      __O  uint32_t   PENDRESET : 32; //!<[00] PENDRESET
    } B;
    __O  uint32_t  R;
    explicit IPRR2_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IPRR2_DEF r;
      R = f (r);
    }
  };
  union IPRR3_DEF     {  //!< Interrupt Pending Clear Register
    struct {
      __O  uint32_t   PENDRESET : 32; //!<[00] PENDRESET
    } B;
    __O  uint32_t  R;
    explicit IPRR3_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IPRR3_DEF r;
      R = f (r);
    }
  };
  union IPRR4_DEF     {  //!< Interrupt Pending Clear Register
    struct {
      __O  uint32_t   PENDRESET :  8; //!<[00] PENDRESET
    } B;
    __O  uint32_t  R;
    explicit IPRR4_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IPRR4_DEF r;
      R = f (r);
    }
  };
  union IACTR1_DEF    {  //!< Interrupt ACTIVE Register
    struct {
           uint32_t   UNUSED0    :  2; //!<[00] 
      __O  uint32_t   IACTS2_3   :  2; //!<[02] IACTS
           uint32_t   UNUSED1    :  8; //!<[04] 
      __O  uint32_t   IACTS12_31 : 20; //!<[12] IACTS
    } B;
    __O  uint32_t  R;
    explicit IACTR1_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IACTR1_DEF r;
      R = f (r);
    }
  };
  union IACTR2_DEF    {  //!< Interrupt ACTIVE Register
    struct {
      __O  uint32_t   IACTS : 32; //!<[00] IACTS
    } B;
    __O  uint32_t  R;
    explicit IACTR2_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IACTR2_DEF r;
      R = f (r);
    }
  };
  union IACTR3_DEF    {  //!< Interrupt ACTIVE Register
    struct {
      __O  uint32_t   IACTS : 32; //!<[00] IACTS
    } B;
    __O  uint32_t  R;
    explicit IACTR3_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IACTR3_DEF r;
      R = f (r);
    }
  };
  union IACTR4_DEF    {  //!< Interrupt ACTIVE Register
    struct {
      __O  uint32_t   IACTS :  8; //!<[00] IACTS
    } B;
    __O  uint32_t  R;
    explicit IACTR4_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      IACTR4_DEF r;
      R = f (r);
    }
  };
  union SCTLR_DEF     {  //!< System Control Register
    struct {
           ONE_BIT    UNUSED0     :  1; //!<[00] 
      __IO ONE_BIT    SLEEPONEXIT :  1; //!<[01] SLEEPONEXIT
      __IO ONE_BIT    SLEEPDEEP   :  1; //!<[02] SLEEPDEEP
      __IO ONE_BIT    WFITOWFE    :  1; //!<[03] WFITOWFE
      __IO ONE_BIT    SEVONPEND   :  1; //!<[04] SEVONPEND
      __IO ONE_BIT    SETEVENT    :  1; //!<[05] SETEVENT
           uint32_t   UNUSED1     : 25; //!<[06] 
      __IO ONE_BIT    SYSRESET    :  1; //!<[31] SYSRESET
    } B;
    __IO uint32_t  R;
    explicit SCTLR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      SCTLR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      SCTLR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union STK_CTLR_DEF  {  //!< System counter control register
    struct {
      __IO ONE_BIT    STE     :  1; //!<[00] System counter enable
      __IO ONE_BIT    STIE    :  1; //!<[01] System counter interrupt enable
      __IO ONE_BIT    STCLK   :  1; //!<[02] System selects the clock source
      __IO ONE_BIT    STRE    :  1; //!<[03] System reload register
      __IO ONE_BIT    MODE    :  1; //!<[04] System Mode
      __IO ONE_BIT    INIT    :  1; //!<[05] System Initialization update
           uint32_t   UNUSED0 : 25; //!<[06] 
      __IO ONE_BIT    SWIE    :  1; //!<[31] System software triggered interrupts enable
    } B;
    __IO uint32_t  R;
    explicit STK_CTLR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      STK_CTLR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      STK_CTLR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union STK_SR_DEF    {  //!< System START
    struct {
      __IO ONE_BIT  CNTIF :  1; //!<[00] CNTIF
    } B;
    __IO uint32_t  R;
    explicit STK_SR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      STK_SR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      STK_SR_DEF r; r.R = R;
      R = f (r);
    }
  };
  union STK_CNTL_DEF  {  //!< System counter low register
    struct {
      __IO uint32_t   CNTL : 32; //!<[00] CNTL
    } B;
    __IO uint32_t  R;
    explicit STK_CNTL_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      STK_CNTL_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      STK_CNTL_DEF r; r.R = R;
      R = f (r);
    }
  };
  union STK_CMPLR_DEF {  //!< System compare low register
    struct {
      __IO uint32_t   CMPL : 32; //!<[00] CMPL
    } B;
    __IO uint32_t  R;
    explicit STK_CMPLR_DEF () noexcept { R = 0x00000000u; }
    template<typename F> void setbit (F f) volatile {
      STK_CMPLR_DEF r;
      R = f (r);
    }
    template<typename F> void modify (F f) volatile {
      STK_CMPLR_DEF r; r.R = R;
      R = f (r);
    }
  };
  // PERIPHERAL PFIC REGISTERS INSTANCES
  __I  ISR1_DEF                 ISR1 ;  //!< [0000](04)[0x0000000C]
  __I  ISR2_DEF                 ISR2 ;  //!< [0004](04)[0x00000000]
  __I  ISR3_DEF                 ISR3 ;  //!< [0008](04)[0x00000000]
  __I  ISR4_DEF                 ISR4 ;  //!< [000c](04)[0x00000000]
       uint32_t            UNUSED0 [4];  //!< [0010](10)[0xFFFFFFFF]
  __I  IPR1_DEF                 IPR1 ;  //!< [0020](04)[0x00000000]
  __I  IPR2_DEF                 IPR2 ;  //!< [0024](04)[0x00000000]
  __I  IPR3_DEF                 IPR3 ;  //!< [0028](04)[0x00000000]
  __I  IPR4_DEF                 IPR4 ;  //!< [002c](04)[0x00000000]
       uint32_t            UNUSED1 [4];  //!< [0030](10)[0xFFFFFFFF]
  __IO ITHRESDR_DEF         ITHRESDR ;  //!< [0040](04)[0x00000000]
       uint32_t            UNUSED2 ;  //!< [0044](04)[0xFFFFFFFF]
  __IO CFGR_DEF                 CFGR ;  //!< [0048](04)[0x00000000]
  __I  GISR_DEF                 GISR ;  //!< [004c](04)[0x00000000]
  __IO VTFIDR_DEF             VTFIDR ;  //!< [0050](04)[0x00000000]
       uint32_t            UNUSED3 [3];  //!< [0054](0c)[0xFFFFFFFF]
  __IO VTFADDRR0_DEF       VTFADDRR0 ;  //!< [0060](04)[0x00000000]
  __IO VTFADDRR1_DEF       VTFADDRR1 ;  //!< [0064](04)[0x00000000]
  __IO VTFADDRR2_DEF       VTFADDRR2 ;  //!< [0068](04)[0x00000000]
  __IO VTFADDRR3_DEF       VTFADDRR3 ;  //!< [006c](04)[0x00000000]
       uint32_t            UNUSED4 [36];  //!< [0070](90)[0xFFFFFFFF]
  __O  IENR1_DEF               IENR1 ;  //!< [0100](04)[0x00000000]
  __O  IENR2_DEF               IENR2 ;  //!< [0104](04)[0x00000000]
  __O  IENR3_DEF               IENR3 ;  //!< [0108](04)[0x00000000]
  __O  IENR4_DEF               IENR4 ;  //!< [010c](04)[0x00000000]
       uint32_t            UNUSED5 [28];  //!< [0110](70)[0xFFFFFFFF]
  __O  IRER1_DEF               IRER1 ;  //!< [0180](04)[0x00000000]
  __O  IRER2_DEF               IRER2 ;  //!< [0184](04)[0x00000000]
  __O  IRER3_DEF               IRER3 ;  //!< [0188](04)[0x00000000]
  __O  IRER4_DEF               IRER4 ;  //!< [018c](04)[0x00000000]
       uint32_t            UNUSED6 [28];  //!< [0190](70)[0xFFFFFFFF]
  __O  IPSR1_DEF               IPSR1 ;  //!< [0200](04)[0x00000000]
  __O  IPSR2_DEF               IPSR2 ;  //!< [0204](04)[0x00000000]
  __O  IPSR3_DEF               IPSR3 ;  //!< [0208](04)[0x00000000]
  __O  IPSR4_DEF               IPSR4 ;  //!< [020c](04)[0x00000000]
       uint32_t            UNUSED7 [28];  //!< [0210](70)[0xFFFFFFFF]
  __O  IPRR1_DEF               IPRR1 ;  //!< [0280](04)[0x00000000]
  __O  IPRR2_DEF               IPRR2 ;  //!< [0284](04)[0x00000000]
  __O  IPRR3_DEF               IPRR3 ;  //!< [0288](04)[0x00000000]
  __O  IPRR4_DEF               IPRR4 ;  //!< [028c](04)[0x00000000]
       uint32_t            UNUSED8 [28];  //!< [0290](70)[0xFFFFFFFF]
  __O  IACTR1_DEF             IACTR1 ;  //!< [0300](04)[0x00000000]
  __O  IACTR2_DEF             IACTR2 ;  //!< [0304](04)[0x00000000]
  __O  IACTR3_DEF             IACTR3 ;  //!< [0308](04)[0x00000000]
  __O  IACTR4_DEF             IACTR4 ;  //!< [030c](04)[0x00000000]
       uint32_t            UNUSED9 [60];  //!< [0310](f0)[0xFFFFFFFF]
  __IO uint8_t             IPRIOR0 ;  //!< [0400](01)[0x00000000]
  __IO uint8_t             IPRIOR1 ;  //!< [0401](01)[0x00000000]
  __IO uint8_t             IPRIOR2 ;  //!< [0402](01)[0x00000000]
  __IO uint8_t             IPRIOR3 ;  //!< [0403](01)[0x00000000]
  __IO uint8_t             IPRIOR4 ;  //!< [0404](01)[0x00000000]
  __IO uint8_t             IPRIOR5 ;  //!< [0405](01)[0x00000000]
  __IO uint8_t             IPRIOR6 ;  //!< [0406](01)[0x00000000]
  __IO uint8_t             IPRIOR7 ;  //!< [0407](01)[0x00000000]
  __IO uint8_t             IPRIOR8 ;  //!< [0408](01)[0x00000000]
  __IO uint8_t             IPRIOR9 ;  //!< [0409](01)[0x00000000]
  __IO uint8_t           IPRIOR10 ;  //!< [040a](01)[0x00000000]
  __IO uint8_t           IPRIOR11 ;  //!< [040b](01)[0x00000000]
  __IO uint8_t           IPRIOR12 ;  //!< [040c](01)[0x00000000]
  __IO uint8_t           IPRIOR13 ;  //!< [040d](01)[0x00000000]
  __IO uint8_t           IPRIOR14 ;  //!< [040e](01)[0x00000000]
  __IO uint8_t           IPRIOR15 ;  //!< [040f](01)[0x00000000]
  __IO uint8_t           IPRIOR16 ;  //!< [0410](01)[0x00000000]
  __IO uint8_t           IPRIOR17 ;  //!< [0411](01)[0x00000000]
  __IO uint8_t           IPRIOR18 ;  //!< [0412](01)[0x00000000]
  __IO uint8_t           IPRIOR19 ;  //!< [0413](01)[0x00000000]
  __IO uint8_t           IPRIOR20 ;  //!< [0414](01)[0x00000000]
  __IO uint8_t           IPRIOR21 ;  //!< [0415](01)[0x00000000]
  __IO uint8_t           IPRIOR22 ;  //!< [0416](01)[0x00000000]
  __IO uint8_t           IPRIOR23 ;  //!< [0417](01)[0x00000000]
  __IO uint8_t           IPRIOR24 ;  //!< [0418](01)[0x00000000]
  __IO uint8_t           IPRIOR25 ;  //!< [0419](01)[0x00000000]
  __IO uint8_t           IPRIOR26 ;  //!< [041a](01)[0x00000000]
  __IO uint8_t           IPRIOR27 ;  //!< [041b](01)[0x00000000]
  __IO uint8_t           IPRIOR28 ;  //!< [041c](01)[0x00000000]
  __IO uint8_t           IPRIOR29 ;  //!< [041d](01)[0x00000000]
  __IO uint8_t           IPRIOR30 ;  //!< [041e](01)[0x00000000]
  __IO uint8_t           IPRIOR31 ;  //!< [041f](01)[0x00000000]
  __IO uint8_t           IPRIOR32 ;  //!< [0420](01)[0x00000000]
  __IO uint8_t           IPRIOR33 ;  //!< [0421](01)[0x00000000]
  __IO uint8_t           IPRIOR34 ;  //!< [0422](01)[0x00000000]
  __IO uint8_t           IPRIOR35 ;  //!< [0423](01)[0x00000000]
  __IO uint8_t           IPRIOR36 ;  //!< [0424](01)[0x00000000]
  __IO uint8_t           IPRIOR37 ;  //!< [0425](01)[0x00000000]
  __IO uint8_t           IPRIOR38 ;  //!< [0426](01)[0x00000000]
  __IO uint8_t           IPRIOR39 ;  //!< [0427](01)[0x00000000]
  __IO uint8_t           IPRIOR40 ;  //!< [0428](01)[0x00000000]
  __IO uint8_t           IPRIOR41 ;  //!< [0429](01)[0x00000000]
  __IO uint8_t           IPRIOR42 ;  //!< [042a](01)[0x00000000]
  __IO uint8_t           IPRIOR43 ;  //!< [042b](01)[0x00000000]
  __IO uint8_t           IPRIOR44 ;  //!< [042c](01)[0x00000000]
  __IO uint8_t           IPRIOR45 ;  //!< [042d](01)[0x00000000]
  __IO uint8_t           IPRIOR46 ;  //!< [042e](01)[0x00000000]
  __IO uint8_t           IPRIOR47 ;  //!< [042f](01)[0x00000000]
  __IO uint8_t           IPRIOR48 ;  //!< [0430](01)[0x00000000]
  __IO uint8_t           IPRIOR49 ;  //!< [0431](01)[0x00000000]
  __IO uint8_t           IPRIOR50 ;  //!< [0432](01)[0x00000000]
  __IO uint8_t           IPRIOR51 ;  //!< [0433](01)[0x00000000]
  __IO uint8_t           IPRIOR52 ;  //!< [0434](01)[0x00000000]
  __IO uint8_t           IPRIOR53 ;  //!< [0435](01)[0x00000000]
  __IO uint8_t           IPRIOR54 ;  //!< [0436](01)[0x00000000]
  __IO uint8_t           IPRIOR55 ;  //!< [0437](01)[0x00000000]
  __IO uint8_t           IPRIOR56 ;  //!< [0438](01)[0x00000000]
  __IO uint8_t           IPRIOR57 ;  //!< [0439](01)[0x00000000]
  __IO uint8_t           IPRIOR58 ;  //!< [043a](01)[0x00000000]
  __IO uint8_t           IPRIOR59 ;  //!< [043b](01)[0x00000000]
  __IO uint8_t           IPRIOR60 ;  //!< [043c](01)[0x00000000]
  __IO uint8_t           IPRIOR61 ;  //!< [043d](01)[0x00000000]
  __IO uint8_t           IPRIOR62 ;  //!< [043e](01)[0x00000000]
  __IO uint8_t           IPRIOR63 ;  //!< [043f](01)[0x00000000]
       uint32_t          UNUSED10 [564];  //!< [0440](8d0)[0xFFFFFFFF]
  __IO SCTLR_DEF               SCTLR ;  //!< [0d10](04)[0x00000000]
       uint32_t          UNUSED11 [187];  //!< [0d14](2ec)[0xFFFFFFFF]
  __IO STK_CTLR_DEF         STK_CTLR ;  //!< [1000](04)[0x00000000]
  __IO STK_SR_DEF             STK_SR ;  //!< [1004](04)[0x00000000]
  __IO STK_CNTL_DEF         STK_CNTL ;  //!< [1008](04)[0x00000000]
       uint32_t          UNUSED12 ;  //!< [100c](04)[0xFFFFFFFF]
  __IO STK_CMPLR_DEF       STK_CMPLR ;  //!< [1010](04)[0x00000000]
}; /* total size = 0x1100, struct size = 0x1014 */
static ESIG_Type   & ESIG   = * reinterpret_cast<ESIG_Type   * const> (0x1ffff7e0);
static TIM2_Type   & TIM2   = * reinterpret_cast<TIM2_Type   * const> (0x40000000);
static WWDG_Type   & WWDG   = * reinterpret_cast<WWDG_Type   * const> (0x40002c00);
static IWDG_Type   & IWDG   = * reinterpret_cast<IWDG_Type   * const> (0x40003000);
static I2C1_Type   & I2C1   = * reinterpret_cast<I2C1_Type   * const> (0x40005400);
static PWR_Type    & PWR    = * reinterpret_cast<PWR_Type    * const> (0x40007000);
static AFIO_Type   & AFIO   = * reinterpret_cast<AFIO_Type   * const> (0x40010000);
static EXTI_Type   & EXTI   = * reinterpret_cast<EXTI_Type   * const> (0x40010400);
static GPIOA_Type  & GPIOA  = * reinterpret_cast<GPIOA_Type  * const> (0x40010800);
static GPIOA_Type  & GPIOC  = * reinterpret_cast<GPIOA_Type  * const> (0x40011000);
static GPIOA_Type  & GPIOD  = * reinterpret_cast<GPIOA_Type  * const> (0x40011400);
static ADC1_Type   & ADC1   = * reinterpret_cast<ADC1_Type   * const> (0x40012400);
static TIM1_Type   & TIM1   = * reinterpret_cast<TIM1_Type   * const> (0x40012c00);
static SPI1_Type   & SPI1   = * reinterpret_cast<SPI1_Type   * const> (0x40013000);
static USART1_Type & USART1 = * reinterpret_cast<USART1_Type * const> (0x40013800);
static DMA1_Type   & DMA1   = * reinterpret_cast<DMA1_Type   * const> (0x40020000);
static RCC_Type    & RCC    = * reinterpret_cast<RCC_Type    * const> (0x40021000);
static FLASH_Type  & FLASH  = * reinterpret_cast<FLASH_Type  * const> (0x40022000);
static EXTEND_Type & EXTEND = * reinterpret_cast<EXTEND_Type * const> (0x40023800);
static DBG_Type    & DBG    = * reinterpret_cast<DBG_Type    * const> (0xe000d000);
static PFIC_Type   & PFIC   = * reinterpret_cast<PFIC_Type   * const> (0xe000e000);

static_assert (sizeof(struct ESIG_Type) == 20, "size error ESIG");
static_assert (sizeof(struct TIM2_Type) == 80, "size error TIM2");
static_assert (sizeof(struct WWDG_Type) == 12, "size error WWDG");
static_assert (sizeof(struct IWDG_Type) == 16, "size error IWDG");
static_assert (sizeof(struct I2C1_Type) == 32, "size error I2C1");
static_assert (sizeof(struct PWR_Type) == 20, "size error PWR");
static_assert (sizeof(struct AFIO_Type) == 12, "size error AFIO");
static_assert (sizeof(struct EXTI_Type) == 24, "size error EXTI");
static_assert (sizeof(struct GPIOA_Type) == 28, "size error GPIOA");
static_assert (sizeof(struct ADC1_Type) == 84, "size error ADC1");
static_assert (sizeof(struct TIM1_Type) == 80, "size error TIM1");
static_assert (sizeof(struct SPI1_Type) == 40, "size error SPI1");
static_assert (sizeof(struct USART1_Type) == 28, "size error USART1");
static_assert (sizeof(struct DMA1_Type) == 144, "size error DMA1");
static_assert (sizeof(struct RCC_Type) == 40, "size error RCC");
static_assert (sizeof(struct FLASH_Type) == 44, "size error FLASH");
static_assert (sizeof(struct EXTEND_Type) == 8, "size error EXTEND");
static_assert (sizeof(struct DBG_Type) == 8, "size error DBG");
static_assert (sizeof(struct PFIC_Type) == 4116, "size error PFIC");
#if 1
/* Interrupts : conflicts cmsis part - use copy / paste */
enum IRQn {
  /******  RISC-V Processor Exceptions Numbers *************************************/
  NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt                             */
  EXC_IRQn = 3,            /* 3 Exception Interrupt                                */
  SysTicK_IRQn = 12,       /* 12 System timer Interrupt                            */
  Software_IRQn = 14,      /* 14 software Interrupt                                */
  
  WWDG_IRQn             =  16, //!< Window Watchdog interrupt
  PVD_IRQn              =  17, //!< PVD through EXTI line detection interrupt
  FLASH_IRQn            =  18, //!< Flash global interrupt
  RCC_IRQn              =  19, //!< RCC global interrupt
  EXTI7_0_IRQn          =  20, //!< EXTI Line[7:0] interrupt
  AWU_IRQn              =  21, //!< AWU global interrupt
  DMA1_Channel1_IRQn    =  22, //!< DMA1 Channel1 global interrupt
  DMA1_Channel2_IRQn    =  23, //!< DMA1 Channel2 global interrupt
  DMA1_Channel3_IRQn    =  24, //!< DMA1 Channel3 global interrupt
  DMA1_Channel4_IRQn    =  25, //!< DMA1 Channel4 global interrupt
  DMA1_Channel5_IRQn    =  26, //!< DMA1 Channel5 global interrupt
  DMA1_Channel6_IRQn    =  27, //!< DMA1 Channel6 global interrupt
  DMA1_Channel7_IRQn    =  28, //!< DMA1 Channel7 global interrupt
  ADC_IRQn              =  29, //!< ADC global interrupt
  I2C1_EV_IRQn          =  30, //!< I2C1 event interrupt
  I2C1_ER_IRQn          =  31, //!< I2C1 error interrupt
  USART1_IRQn           =  32, //!< USART1 global interrupt
  SPI1_IRQn             =  33, //!< SPI1 global interrupt
  TIM1_BRK_IRQn         =  34, //!< TIM1 Break interrupt
  TIM1_UP_IRQn          =  35, //!< TIM1 Update interrupt
  TIM1_TRG_COM_IRQn     =  36, //!< TIM1 Trigger and Commutation interrupts
  TIM1_CC_IRQn          =  37, //!< TIM1 Capture Compare interrupt
  TIM2_IRQn             =  38, //!< TIM2 global interrupt
};
#endif
#endif