WCH Ltd. WCH CH32V00xxx 1.0 CH32V00xxx View File 8 32 0x20 0x0 0xFFFFFFFF PWR Power control PWR 0x40007000 0x0 0x400 registers PVD PVD through EXTI line detection interrupt 17 AWU AWU global interrupt 21 CTLR CTLR Power control register (PWR_CTRL) 0x0 0x20 read-write 0x00000000 PDDS Power Down Deep Sleep 1 1 PVDE Power Voltage Detector Enable 4 1 PLS PVD Level Selection 5 3 CSR CSR Power control state register (PWR_CSR) 0x04 0x20 0x00000000 PVDO PVD Output 2 1 read-only AWUCSR AWUCSR Automatic wake-up control state register (PWR_AWUCSR) 0x08 0x20 0x00000000 AWUEN Automatic wake-up enable 1 1 read-write AWUAPR AWUAPR Automatic wake window comparison value register (PWR_AWUAPR) 0x0C 0x20 0x0000003F AWUAPR AWU window value 0 6 read-write AWUPSC AWUPSC Automatic wake-up prescaler register (PWR_AWUPSC) 0x10 0x20 0x00000000 AWUPSC Wake-up prescaler 0 4 read-write RCC Reset and clock control RCC 0x40021000 0x00 0x400 registers RCC RCC global interrupt 19 CTLR CTLR Clock control register 0x00 0x20 0x00000083 HSION Internal High Speed clock enable 0 1 read-write HSIRDY Internal High Speed clock ready flag 1 1 read-only HSITRIM Internal High Speed clock trimming 3 5 read-write HSICAL Internal High Speed clock Calibration 8 8 read-only HSEON External High Speed clock enable 16 1 read-write HSERDY External High Speed clock ready flag 17 1 read-only HSEBYP External High Speed clock Bypass 18 1 read-write CSSON Clock Security System enable 19 1 read-write PLLON PLL enable 24 1 read-write PLLRDY PLL clock ready flag 25 1 read-only CFGR0 CFGR0 Clock configuration register (RCC_CFGR0) 0x04 0x20 0x00000000 SW System clock Switch 0 2 read-write SWS System Clock Switch Status 2 2 read-only HPRE AHB prescaler 4 4 read-write PPRE1 APB Low speed prescaler (APB1) 8 3 read-write PPRE2 APB High speed prescaler (APB2) 11 3 read-write ADCPRE ADC prescaler 14 2 read-write PLLSRC PLL entry clock source 16 1 read-write MCO Microcontroller clock output 24 3 read-write INTR INTR Clock interrupt register (RCC_INTR) 0x08 0x20 0x00000000 LSIRDYF LSI Ready Interrupt flag 0 1 read-only HSIRDYF HSI Ready Interrupt flag 2 1 read-only HSERDYF HSE Ready Interrupt flag 3 1 read-only PLLRDYF PLL Ready Interrupt flag 4 1 read-only CSSF Clock Security System Interrupt flag 7 1 read-only LSIRDYIE LSI Ready Interrupt Enable 8 1 read-write HSIRDYIE HSI Ready Interrupt Enable 10 1 read-write HSERDYIE HSE Ready Interrupt Enable 11 1 read-write PLLRDYIE PLL Ready Interrupt Enable 12 1 read-write LSIRDYC LSI Ready Interrupt Clear 16 1 write-only HSIRDYC HSI Ready Interrupt Clear 18 1 write-only HSERDYC HSE Ready Interrupt Clear 19 1 write-only PLLRDYC PLL Ready Interrupt Clear 20 1 write-only CSSC Clock security system interrupt clear 23 1 write-only APB2PRSTR APB2PRSTR APB2 peripheral reset register (RCC_APB2PRSTR) 0x0C 0x20 read-write 0x00000000 AFIORST Alternate function I/O reset 0 1 IOPARST IO port A reset 2 1 IOPCRST IO port C reset 4 1 IOPDRST IO port D reset 5 1 ADC1RST ADC 1 interface reset 9 1 TIM1RST TIM1 timer reset 11 1 SPI1RST SPI 1 reset 12 1 USART1RST USART1 reset 14 1 APB1PRSTR APB1PRSTR APB1 peripheral reset register (RCC_APB1PRSTR) 0x10 0x20 read-write 0x00000000 WWDGRST Window watchdog reset 11 1 I2C1RST I2C1 reset 21 1 PWRRST Power interface reset 28 1 AHBPCENR AHBPCENR AHB Peripheral Clock enable register (RCC_AHBPCENR) 0x14 0x20 read-write 0x00000004 DMA1EN DMA clock enable 0 1 SRAMEN SRAM interface clock enable 2 1 APB2PCENR APB2PCENR APB2 peripheral clock enable register (RCC_APB2PCENR) 0x18 0x20 read-write 0x00000000 AFIOEN Alternate function I/O clock enable 0 1 IOPAEN I/O port A clock enable 2 1 IOPCEN I/O port C clock enable 4 1 IOPDEN I/O port D clock enable 5 1 ADC1EN ADC1 interface clock enable 9 1 TIM1EN TIM1 Timer clock enable 11 1 SPI1EN SPI 1 clock enable 12 1 USART1EN USART1 clock enable 14 1 APB1PCENR APB1PCENR APB1 peripheral clock enable register (RCC_APB1PCENR) 0x1C 0x20 read-write 0x00000000 TIM2EN Timer 2 clock enable 0 1 WWDGEN Window watchdog clock enable 11 1 I2C1EN I2C 1 clock enable 21 1 PWREN Power interface clock enable 28 1 RSTSCKR RSTSCKR Control/status register (RCC_RSTSCKR) 0x24 0x20 0x0C000000 LSION Internal low speed oscillator enable 0 1 read-write LSIRDY Internal low speed oscillator ready 1 1 read-only RMVF Remove reset flag 24 1 read-write PINRSTF PIN reset flag 26 1 read-only PORRSTF POR/PDR reset flag 27 1 read-only SFTRSTF Software reset flag 28 1 read-only IWDGRSTF Independent watchdog reset flag 29 1 read-only WWDGRSTF Window watchdog reset flag 30 1 read-only LPWRRSTF Low-power reset flag 31 1 read-only EXTEND Extend configuration EXTEND 0x40023800 0x00 0x400 registers EXTEND_CTR EXTEND Configure the extended control register 0x00 0x20 0x00000040 PLL_CFG Configure the PLL clock delay time 0 4 read-write LOCKUP_EN LOCKUP_Enable 6 1 read-write LOCKUP_RESET LOCKUP RESET 7 1 read-write LDO_TRIM LDO_TRIM 10 1 read-write FLASH_CLK_TRIM FLASH clock trimming 11 3 read-write WR_EN Control Register write enable 14 1 read-write WR_LOCK Control Register write lock 15 1 read-write OPA_EN OPA Enalbe 16 1 read-write OPA_NSEL OPA negative end channel selection 17 1 read-write OPA_PSEL OPA positive end channel selection 18 1 read-write EXTEND_KR EXTEND Configure the extended key register 0x04 0x20 0x00000000 KEY Write key value 0 32 write-only GPIOA General purpose I/O GPIO 0x40010800 0x0 0x400 registers CFGLR CFGLR Port configuration register low (GPIOn_CFGLR) 0x0 0x20 read-write 0x44444444 MODE0 Port n.0 mode bits 0 2 CNF0 Port n.0 configuration bits 2 2 MODE1 Port n.1 mode bits 4 2 CNF1 Port n.1 configuration bits 6 2 MODE2 Port n.2 mode bits 8 2 CNF2 Port n.2 configuration bits 10 2 MODE3 Port n.3 mode bits 12 2 CNF3 Port n.3 configuration bits 14 2 MODE4 Port n.4 mode bits 16 2 CNF4 Port n.4 configuration bits 18 2 MODE5 Port n.5 mode bits 20 2 CNF5 Port n.5 configuration bits 22 2 MODE6 Port n.6 mode bits 24 2 CNF6 Port n.6 configuration bits 26 2 MODE7 Port n.7 mode bits 28 2 CNF7 Port n.7 configuration bits 30 2 INDR INDR Port input data register (GPIOn_INDR) 0x8 0x20 read-only 0x00000000 IDR0 Port input data 0 1 IDR1 Port input data 1 1 IDR2 Port input data 2 1 IDR3 Port input data 3 1 IDR4 Port input data 4 1 IDR5 Port input data 5 1 IDR6 Port input data 6 1 IDR7 Port input data 7 1 OUTDR OUTDR Port output data register (GPIOn_OUTDR) 0xC 0x20 read-write 0x00000000 ODR0 Port output data 0 1 ODR1 Port output data 1 1 ODR2 Port output data 2 1 ODR3 Port output data 3 1 ODR4 Port output data 4 1 ODR5 Port output data 5 1 ODR6 Port output data 6 1 ODR7 Port output data 7 1 BSHR BSHR Port bit set/reset register (GPIOn_BSHR) 0x10 0x20 write-only 0x00000000 BS0 Set bit 0 0 1 BS1 Set bit 1 1 1 BS2 Set bit 1 2 1 BS3 Set bit 3 3 1 BS4 Set bit 4 4 1 BS5 Set bit 5 5 1 BS6 Set bit 6 6 1 BS7 Set bit 7 7 1 BR0 Reset bit 0 16 1 BR1 Reset bit 1 17 1 BR2 Reset bit 2 18 1 BR3 Reset bit 3 19 1 BR4 Reset bit 4 20 1 BR5 Reset bit 5 21 1 BR6 Reset bit 6 22 1 BR7 Reset bit 7 23 1 BCR BCR Port bit reset register (GPIOn_BCR) 0x14 0x20 write-only 0x00000000 BR0 Reset bit 0 0 1 BR1 Reset bit 1 1 1 BR2 Reset bit 1 2 1 BR3 Reset bit 3 3 1 BR4 Reset bit 4 4 1 BR5 Reset bit 5 5 1 BR6 Reset bit 6 6 1 BR7 Reset bit 7 7 1 LCKR LCKR Port configuration lock register 0x18 0x20 read-write 0x00000000 LCK0 Port A Lock bit 0 0 1 LCK1 Port A Lock bit 1 1 1 LCK2 Port A Lock bit 2 2 1 LCK3 Port A Lock bit 3 3 1 LCK4 Port A Lock bit 4 4 1 LCK5 Port A Lock bit 5 5 1 LCK6 Port A Lock bit 6 6 1 LCK7 Port A Lock bit 7 7 1 LCKK Lock key 8 1 GPIOC 0x40011000 GPIOD 0x40011400 AFIO Alternate function I/O AFIO 0x40010000 0x0 0x400 registers PCFR PCFR AF remap and debug I/O configuration register (AFIO_PCFR) 0x4 0x20 0x00000000 SPI1RM SPI1 remapping 0 1 read-write I2C1RM I2C1 remapping 1 1 read-write USART1RM USART1 remapping 2 1 read-write TIM1RM TIM1 remapping 6 2 read-write TIM2RM TIM2 remapping 8 2 read-write PA12RM Port A1/Port A2 mapping on OSCIN/OSCOUT 15 1 read-write ADC1_ETRGINJ_RM ADC 1 External trigger injected conversion remapping 17 1 read-write ADC1_ETRGREG_RM ADC 1 external trigger regular conversion remapping 18 1 read-write USART1REMAP1 USART1 remapping 21 1 read-write I2C1REMAP1 I2C1 remapping 22 1 read-write TIM1_IREMAP TIM1_CH1 channel selection 23 1 read-write SWCFG Serial wire JTAG configuration 24 3 write-only EXTICR EXTICR External interrupt configuration register (AFIO_EXTICR) 0x08 0x20 read-write 0x00000000 EXTI0 EXTI0 configuration 0 2 EXTI1 EXTI1 configuration 2 2 EXTI2 EXTI2 configuration 4 2 EXTI3 EXTI3 configuration 6 2 EXTI4 EXTI4 configuration 8 2 EXTI5 EXTI5 configuration 10 2 EXTI6 EXTI6 configuration 12 2 EXTI7 EXTI7 configuration 14 2 EXTI EXTI EXTI 0x40010400 0x00 0x400 registers EXTI7_0 EXTI Line[7:0] interrupt 20 INTENR INTENR Interrupt mask register (EXTI_INTENR) 0x00 0x20 read-write 0x00000000 MR0 Interrupt Mask on line 0 0 1 MR1 Interrupt Mask on line 1 1 1 MR2 Interrupt Mask on line 2 2 1 MR3 Interrupt Mask on line 3 3 1 MR4 Interrupt Mask on line 4 4 1 MR5 Interrupt Mask on line 5 5 1 MR6 Interrupt Mask on line 6 6 1 MR7 Interrupt Mask on line 7 7 1 MR8 Interrupt Mask on line 8 8 1 MR9 Interrupt Mask on line 9 9 1 EVENR EVENR Event mask register (EXTI_EVENR) 0x04 0x20 read-write 0x00000000 MR0 Event Mask on line 0 0 1 MR1 Event Mask on line 1 1 1 MR2 Event Mask on line 2 2 1 MR3 Event Mask on line 3 3 1 MR4 Event Mask on line 4 4 1 MR5 Event Mask on line 5 5 1 MR6 Event Mask on line 6 6 1 MR7 Event Mask on line 7 7 1 MR8 Event Mask on line 8 8 1 MR9 Event Mask on line 9 9 1 RTENR RTENR Rising Trigger selection register (EXTI_RTENR) 0x08 0x20 read-write 0x00000000 TR0 Rising trigger event configuration of line 0 0 1 TR1 Rising trigger event configuration of line 1 1 1 TR2 Rising trigger event configuration of line 2 2 1 TR3 Rising trigger event configuration of line 3 3 1 TR4 Rising trigger event configuration of line 4 4 1 TR5 Rising trigger event configuration of line 5 5 1 TR6 Rising trigger event configuration of line 6 6 1 TR7 Rising trigger event configuration of line 7 7 1 TR8 Rising trigger event configuration of line 8 8 1 TR9 Rising trigger event configuration of line 9 9 1 FTENR FTENR Falling Trigger selection register (EXTI_FTENR) 0xC 0x20 read-write 0x00000000 TR0 Falling trigger event configuration of line 0 0 1 TR1 Falling trigger event configuration of line 1 1 1 TR2 Falling trigger event configuration of line 2 2 1 TR3 Falling trigger event configuration of line 3 3 1 TR4 Falling trigger event configuration of line 4 4 1 TR5 Falling trigger event configuration of line 5 5 1 TR6 Falling trigger event configuration of line 6 6 1 TR7 Falling trigger event configuration of line 7 7 1 TR8 Falling trigger event configuration of line 8 8 1 TR9 Falling trigger event configuration of line 9 9 1 SWIEVR SWIEVR Software interrupt event register (EXTI_SWIEVR) 0x10 0x20 read-write 0x00000000 SWIER0 Software Interrupt on line 0 0 1 SWIER1 Software Interrupt on line 1 1 1 SWIER2 Software Interrupt on line 2 2 1 SWIER3 Software Interrupt on line 3 3 1 SWIER4 Software Interrupt on line 4 4 1 SWIER5 Software Interrupt on line 5 5 1 SWIER6 Software Interrupt on line 6 6 1 SWIER7 Software Interrupt on line 7 7 1 SWIER8 Software Interrupt on line 8 8 1 SWIER9 Software Interrupt on line 9 9 1 INTFR INTFR Pending register (EXTI_INTFR) 0x14 0x20 read-write 0x00000000 PR0 Pending bit 0 0 1 PR1 Pending bit 1 1 1 PR2 Pending bit 2 2 1 PR3 Pending bit 3 3 1 PR4 Pending bit 4 4 1 PR5 Pending bit 5 5 1 PR6 Pending bit 6 6 1 PR7 Pending bit 7 7 1 PR8 Pending bit 8 8 1 PR9 Pending bit 9 9 1 DMA1 DMA1 controller DMA1 0x40020000 0x0 0x400 registers DMA1_Channel1 DMA1 Channel1 global interrupt 22 DMA1_Channel2 DMA1 Channel2 global interrupt 23 DMA1_Channel3 DMA1 Channel3 global interrupt 24 DMA1_Channel4 DMA1 Channel4 global interrupt 25 DMA1_Channel5 DMA1 Channel5 global interrupt 26 DMA1_Channel6 DMA1 Channel6 global interrupt 27 DMA1_Channel7 DMA1 Channel7 global interrupt 28 INTFR INTFR DMA interrupt status register (DMA_INTFR) 0x0 0x20 read-only 0x00000000 GIF1 Channel 1 Global interrupt flag 0 1 TCIF1 Channel 1 Transfer Complete flag 1 1 HTIF1 Channel 1 Half Transfer Complete flag 2 1 TEIF1 Channel 1 Transfer Error flag 3 1 GIF2 Channel 2 Global interrupt flag 4 1 TCIF2 Channel 2 Transfer Complete flag 5 1 HTIF2 Channel 2 Half Transfer Complete flag 6 1 TEIF2 Channel 2 Transfer Error flag 7 1 GIF3 Channel 3 Global interrupt flag 8 1 TCIF3 Channel 3 Transfer Complete flag 9 1 HTIF3 Channel 3 Half Transfer Complete flag 10 1 TEIF3 Channel 3 Transfer Error flag 11 1 GIF4 Channel 4 Global interrupt flag 12 1 TCIF4 Channel 4 Transfer Complete flag 13 1 HTIF4 Channel 4 Half Transfer Complete flag 14 1 TEIF4 Channel 4 Transfer Error flag 15 1 GIF5 Channel 5 Global interrupt flag 16 1 TCIF5 Channel 5 Transfer Complete flag 17 1 HTIF5 Channel 5 Half Transfer Complete flag 18 1 TEIF5 Channel 5 Transfer Error flag 19 1 GIF6 Channel 6 Global interrupt flag 20 1 TCIF6 Channel 6 Transfer Complete flag 21 1 HTIF6 Channel 6 Half Transfer Complete flag 22 1 TEIF6 Channel 6 Transfer Error flag 23 1 GIF7 Channel 7 Global interrupt flag 24 1 TCIF7 Channel 7 Transfer Complete flag 25 1 HTIF7 Channel 7 Half Transfer Complete flag 26 1 TEIF7 Channel 7 Transfer Error flag 27 1 INTFCR INTFCR DMA interrupt flag clear register (DMA_INTFCR) 0x4 0x20 write-only 0x00000000 CGIF1 Channel 1 Global interrupt clear 0 1 CGIF2 Channel 2 Global interrupt clear 4 1 CGIF3 Channel 3 Global interrupt clear 8 1 CGIF4 Channel 4 Global interrupt clear 12 1 CGIF5 Channel 5 Global interrupt clear 16 1 CGIF6 Channel 6 Global interrupt clear 20 1 CGIF7 Channel 7 Global interrupt clear 24 1 CTCIF1 Channel 1 Transfer Complete clear 1 1 CTCIF2 Channel 2 Transfer Complete clear 5 1 CTCIF3 Channel 3 Transfer Complete clear 9 1 CTCIF4 Channel 4 Transfer Complete clear 13 1 CTCIF5 Channel 5 Transfer Complete clear 17 1 CTCIF6 Channel 6 Transfer Complete clear 21 1 CTCIF7 Channel 7 Transfer Complete clear 25 1 CHTIF1 Channel 1 Half Transfer clear 2 1 CHTIF2 Channel 2 Half Transfer clear 6 1 CHTIF3 Channel 3 Half Transfer clear 10 1 CHTIF4 Channel 4 Half Transfer clear 14 1 CHTIF5 Channel 5 Half Transfer clear 18 1 CHTIF6 Channel 6 Half Transfer clear 22 1 CHTIF7 Channel 7 Half Transfer clear 26 1 CTEIF1 Channel 1 Transfer Error clear 3 1 CTEIF2 Channel 2 Transfer Error clear 7 1 CTEIF3 Channel 3 Transfer Error clear 11 1 CTEIF4 Channel 4 Transfer Error clear 15 1 CTEIF5 Channel 5 Transfer Error clear 19 1 CTEIF6 Channel 6 Transfer Error clear 23 1 CTEIF7 Channel 7 Transfer Error clear 27 1 CFGR1 CFGR1 DMA channel configuration register (DMA_CFGR) 0x8 0x20 read-write 0x00000000 EN Channel enable 0 1 TCIE Transfer complete interrupt enable 1 1 HTIE Half Transfer interrupt enable 2 1 TEIE Transfer error interrupt enable 3 1 DIR Data transfer direction 4 1 CIRC Circular mode 5 1 PINC Peripheral increment mode 6 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 MEM2MEM Memory to memory mode 14 1 CNTR1 CNTR1 DMA channel 1 number of data register 0xC 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 PADDR1 PADDR1 DMA channel 1 peripheral address register 0x10 0x20 read-write 0x00000000 PA Peripheral address 0 32 MADDR1 MADDR1 DMA channel 1 memory address register 0x14 0x20 read-write 0x00000000 MA Memory address 0 32 CFGR2 CFGR2 DMA channel configuration register (DMA_CFGR) 0x1C 0x20 read-write 0x00000000 EN Channel enable 0 1 TCIE Transfer complete interrupt enable 1 1 HTIE Half Transfer interrupt enable 2 1 TEIE Transfer error interrupt enable 3 1 DIR Data transfer direction 4 1 CIRC Circular mode 5 1 PINC Peripheral increment mode 6 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 MEM2MEM Memory to memory mode 14 1 CNTR2 CNTR2 DMA channel 2 number of data register 0x20 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 PADDR2 PADDR2 DMA channel 2 peripheral address register 0x24 0x20 read-write 0x00000000 PA Peripheral address 0 32 MADDR2 MADDR2 DMA channel 2 memory address register 0x28 0x20 read-write 0x00000000 MA Memory address 0 32 CFGR3 CFGR3 DMA channel configuration register (DMA_CFGR) 0x30 0x20 read-write 0x00000000 EN Channel enable 0 1 TCIE Transfer complete interrupt enable 1 1 HTIE Half Transfer interrupt enable 2 1 TEIE Transfer error interrupt enable 3 1 DIR Data transfer direction 4 1 CIRC Circular mode 5 1 PINC Peripheral increment mode 6 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 MEM2MEM Memory to memory mode 14 1 CNTR3 CNTR3 DMA channel 3 number of data register 0x34 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 PADDR3 PADDR3 DMA channel 3 peripheral address register 0x38 0x20 read-write 0x00000000 PA Peripheral address 0 32 MADDR3 MADDR3 DMA channel 3 memory address register 0x3C 0x20 read-write 0x00000000 MA Memory address 0 32 CFGR4 CFGR4 DMA channel configuration register (DMA_CFGR) 0x44 0x20 read-write 0x00000000 EN Channel enable 0 1 TCIE Transfer complete interrupt enable 1 1 HTIE Half Transfer interrupt enable 2 1 TEIE Transfer error interrupt enable 3 1 DIR Data transfer direction 4 1 CIRC Circular mode 5 1 PINC Peripheral increment mode 6 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 MEM2MEM Memory to memory mode 14 1 CNTR4 CNTR4 DMA channel 4 number of data register 0x48 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 PADDR4 PADDR4 DMA channel 4 peripheral address register 0x4C 0x20 read-write 0x00000000 PA Peripheral address 0 32 MADDR4 MADDR4 DMA channel 4 memory address register 0x50 0x20 read-write 0x00000000 MA Memory address 0 32 CFGR5 CFGR5 DMA channel configuration register (DMA_CFGR) 0x58 0x20 read-write 0x00000000 EN Channel enable 0 1 TCIE Transfer complete interrupt enable 1 1 HTIE Half Transfer interrupt enable 2 1 TEIE Transfer error interrupt enable 3 1 DIR Data transfer direction 4 1 CIRC Circular mode 5 1 PINC Peripheral increment mode 6 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 MEM2MEM Memory to memory mode 14 1 CNTR5 CNTR5 DMA channel 5 number of data register 0x5C 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 PADDR5 PADDR5 DMA channel 5 peripheral address register 0x60 0x20 read-write 0x00000000 PA Peripheral address 0 32 MADDR5 MADDR5 DMA channel 5 memory address register 0x64 0x20 read-write 0x00000000 MA Memory address 0 32 CFGR6 CFGR6 DMA channel configuration register (DMA_CFGR) 0x6C 0x20 read-write 0x00000000 EN Channel enable 0 1 TCIE Transfer complete interrupt enable 1 1 HTIE Half Transfer interrupt enable 2 1 TEIE Transfer error interrupt enable 3 1 DIR Data transfer direction 4 1 CIRC Circular mode 5 1 PINC Peripheral increment mode 6 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 MEM2MEM Memory to memory mode 14 1 CNTR6 CNTR6 DMA channel 6 number of data register 0x70 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 PADDR6 PADDR6 DMA channel 6 peripheral address register 0x74 0x20 read-write 0x00000000 PA Peripheral address 0 32 MADDR6 MADDR6 DMA channel 6 memory address register 0x78 0x20 read-write 0x00000000 MA Memory address 0 32 CFGR7 CFGR7 DMA channel configuration register (DMA_CFGR) 0x80 0x20 read-write 0x00000000 EN Channel enable 0 1 TCIE Transfer complete interrupt enable 1 1 HTIE Half Transfer interrupt enable 2 1 TEIE Transfer error interrupt enable 3 1 DIR Data transfer direction 4 1 CIRC Circular mode 5 1 PINC Peripheral increment mode 6 1 MINC Memory increment mode 7 1 PSIZE Peripheral size 8 2 MSIZE Memory size 10 2 PL Channel Priority level 12 2 MEM2MEM Memory to memory mode 14 1 CNTR7 CNTR7 DMA channel 7 number of data register 0x84 0x20 read-write 0x00000000 NDT Number of data to transfer 0 16 PADDR7 PADDR7 DMA channel 7 peripheral address register 0x88 0x20 read-write 0x00000000 PA Peripheral address 0 32 MADDR7 MADDR7 DMA channel 7 memory address register 0x8C 0x20 read-write 0x00000000 MA Memory address 0 32 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers CTLR CTLR Key register (IWDG_CTLR) 0x0 0x20 write-only 0x0000 KEY Key value 0 16 write-only PSCR PSCR Prescaler register (IWDG_PSCR) 0x4 0x20 read-write 0x0000 PR Prescaler divider 0 3 read-write RLDR RLDR Reload register (IWDG_RLDR) 0x8 0x20 read-write 0x0FFF RL Watchdog counter reload value 0 12 read-write STATR STATR Status register (IWDG_SR) 0xC 0x20 read-only 0x0000 PVU Watchdog prescaler value update 0 1 read-only RVU Watchdog counter reload value update 1 1 read-only WWDG Window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window Watchdog interrupt 16 CTLR CTLR Control register (WWDG_CR) 0x0 0x20 read-write 0x007F T 7-bit counter (MSB to LSB) 0 7 read-write WDGA Activation bit 7 1 read-write CFGR CFGR Configuration register (WWDG_CFR) 0x4 0x20 read-write 0x007F W 7-bit window value 0 7 read-write WDGTB Timer Base 7 2 read-write EWI Early Wakeup Interrupt 9 1 read-write STATR STATR Status register (WWDG_SR) 0x8 0x20 read-write 0x0000 WEIF Early Wakeup Interrupt Flag 0 1 read-write TIM1 Advanced timer TIM 0x40012C00 0x0 0x400 registers TIM1_BRK TIM1 Break interrupt 34 TIM1_UP TIM1 Update interrupt 35 TIM1_TRG_COM TIM1 Trigger and Commutation interrupts 36 TIM1_CC TIM1 Capture Compare interrupt 37 CTLR1 CTLR1 control register 1 0x0 0x20 read-write 0x0000 TMR_CAP_LVL_EN Timer capture level indication enable 15 1 TMR_CAP_OV_EN Timer capture value configuration enable 14 1 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CTLR2 CTLR2 control register 2 0x4 0x20 read-write 0x0000 OIS4 Output Idle state 4 14 1 OIS3N Output Idle state 3 13 1 OIS3 Output Idle state 3 12 1 OIS2N Output Idle state 2 11 1 OIS2 Output Idle state 2 10 1 OIS1N Output Idle state 1 9 1 OIS1 Output Idle state 1 8 1 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 CCUS Capture/compare control update selection 2 1 CCPC Capture/compare preloaded control 0 1 SMCFGR SMCFGR slave mode control register 0x8 0x20 0x0000 ETP External trigger polarity 15 1 read-only ECE External clock enable 14 1 read-write ETPS External trigger prescaler 12 2 read-write ETF External trigger filter 8 4 read-write MSM Master/Slave mode 7 1 read-write TS Trigger selection 4 3 read-write SMS Slave mode selection 0 3 read-write DMAINTENR DMAINTENR DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 COMDE COM DMA request enable 13 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 BIE Break interrupt enable 7 1 TIE Trigger interrupt enable 6 1 COMIE COM interrupt enable 5 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 INTFR INTFR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 BIF Break interrupt flag 7 1 TIF Trigger interrupt flag 6 1 COMIF COM interrupt flag 5 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 SWEVGR SWEVGR event generation register 0x14 0x20 write-only 0x0000 BG Break generation 7 1 TG Trigger generation 6 1 COMG Capture/Compare control update generation 5 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CHCTLR1_Output CHCTLR1_Output capture/compare mode register (output mode) 0x18 0x20 read-write 0x0000 OC2CE Output Compare 2 clear enable 15 1 OC2M Output Compare 2 mode 12 3 OC2PE Output Compare 2 preload enable 11 1 OC2FE Output Compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1CE Output Compare 1 clear enable 7 1 OC1M Output Compare 1 mode 4 3 OC1PE Output Compare 1 preload enable 3 1 OC1FE Output Compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CHCTLR1_Input CHCTLR1_Input capture/compare mode register 1 (input mode) CHCTLR1_Output 0x18 0x20 read-write 0x0000 IC2F Input capture 2 filter 12 4 IC2PCS Input capture 2 prescaler 10 2 CC2S Capture/Compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CHCTLR2_Output CHCTLR2_Output capture/compare mode register (output mode) 0x1C 0x20 read-write 0x0000 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 CHCTLR2_Input CHCTLR2_Input capture/compare mode register 2 (input mode) CHCTLR2_Output 0x1C 0x20 read-write 0x0000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3NP Capture/Compare 3 output Polarity 11 1 CC3NE Capture/Compare 3 complementary output enable 10 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2NP Capture/Compare 2 output Polarity 7 1 CC2NE Capture/Compare 2 complementary output enable 6 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1NP Capture/Compare 1 output Polarity 3 1 CC1NE Capture/Compare 1 complementary output enable 2 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x0000 CNT counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ATRLR ATRLR auto-reload register 0x2C 0x20 read-write 0x0000 ATRLR Auto-reload value 0 16 RPTCR RPTCR repetition counter register 0x30 0x20 read-write 0x0000 RPTCR Repetition counter value 0 8 CH1CVR CH1CVR capture/compare register 1 0x34 0x20 read-write 0x0000 CH1CVR Capture/Compare 1 value 0 16 CH2CVR CH2CVR capture/compare register 2 0x38 0x20 read-write 0x0000 CH2CVR Capture/Compare 2 value 0 16 CH3CVR CH3CVR capture/compare register 3 0x3C 0x20 read-write 0x0000 CH3CVR Capture/Compare value 0 16 CH4CVR CH4CVR capture/compare register 4 0x40 0x20 read-write 0x0000 CH4CVR Capture/Compare value 0 16 BDTR BDTR break and dead-time register 0x44 0x20 read-write 0x0000 MOE Main output enable 15 1 AOE Automatic output enable 14 1 BKP Break polarity 13 1 BKE Break enable 12 1 OSSR Off-state selection for Run mode 11 1 OSSI Off-state selection for Idle mode 10 1 LOCK Lock configuration 8 2 DTG Dead-time generator setup 0 8 DMACFGR DMACFGR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAADR DMAADR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAADR DMA register for burst accesses 0 16 TIM2 General purpose timer TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 global interrupt 38 CTLR1 CTLR1 control register 1 0x0 0x20 read-write 0x0000 TMR_CAP_LVL_EN Timer capture level indication enable 15 1 TMR_CAP_OV_EN Timer capture value configuration enable 14 1 CKD Clock division 8 2 ARPE Auto-reload preload enable 7 1 CMS Center-aligned mode selection 5 2 DIR Direction 4 1 OPM One-pulse mode 3 1 URS Update request source 2 1 UDIS Update disable 1 1 CEN Counter enable 0 1 CTLR2 CTLR2 control register 2 0x4 0x20 read-write 0x0000 TI1S TI1 selection 7 1 MMS Master mode selection 4 3 CCDS Capture/compare DMA selection 3 1 SMCFGR SMCFGR slave mode control register 0x8 0x20 read-write 0x0000 ETP External trigger polarity 15 1 ECE External clock enable 14 1 ETPS External trigger prescaler 12 2 ETF External trigger filter 8 4 MSM Master/Slave mode 7 1 TS Trigger selection 4 3 SMS Slave mode selection 0 3 DMAINTENR DMAINTENR DMA/Interrupt enable register 0xC 0x20 read-write 0x0000 TDE Trigger DMA request enable 14 1 CC4DE Capture/Compare 4 DMA request enable 12 1 CC3DE Capture/Compare 3 DMA request enable 11 1 CC2DE Capture/Compare 2 DMA request enable 10 1 CC1DE Capture/Compare 1 DMA request enable 9 1 UDE Update DMA request enable 8 1 TIE Trigger interrupt enable 6 1 CC4IE Capture/Compare 4 interrupt enable 4 1 CC3IE Capture/Compare 3 interrupt enable 3 1 CC2IE Capture/Compare 2 interrupt enable 2 1 CC1IE Capture/Compare 1 interrupt enable 1 1 UIE Update interrupt enable 0 1 INTFR INTFR status register 0x10 0x20 read-write 0x0000 CC4OF Capture/Compare 4 overcapture flag 12 1 CC3OF Capture/Compare 3 overcapture flag 11 1 CC2OF Capture/compare 2 overcapture flag 10 1 CC1OF Capture/Compare 1 overcapture flag 9 1 TIF Trigger interrupt flag 6 1 CC4IF Capture/Compare 4 interrupt flag 4 1 CC3IF Capture/Compare 3 interrupt flag 3 1 CC2IF Capture/Compare 2 interrupt flag 2 1 CC1IF Capture/compare 1 interrupt flag 1 1 UIF Update interrupt flag 0 1 SWEVGR SWEVGR event generation register 0x14 0x20 write-only 0x0000 TG Trigger generation 6 1 CC4G Capture/compare 4 generation 4 1 CC3G Capture/compare 3 generation 3 1 CC2G Capture/compare 2 generation 2 1 CC1G Capture/compare 1 generation 1 1 UG Update generation 0 1 CHCTLR1_Output CHCTLR1_Output capture/compare mode register 1 (output mode) 0x18 0x20 read-write 0x0000 OC2CE Output compare 2 clear enable 15 1 OC2M Output compare 2 mode 12 3 OC2PE Output compare 2 preload enable 11 1 OC2FE Output compare 2 fast enable 10 1 CC2S Capture/Compare 2 selection 8 2 OC1CE Output compare 1 clear enable 7 1 OC1M Output compare 1 mode 4 3 OC1PE Output compare 1 preload enable 3 1 OC1FE Output compare 1 fast enable 2 1 CC1S Capture/Compare 1 selection 0 2 CHCTLR1_Input CHCTLR1_Input capture/compare mode register 1 (input mode) CHCTLR1_Output 0x18 0x20 read-write 0x0000 IC2F Input capture 2 filter 12 4 IC2PSC Input capture 2 prescaler 10 2 CC2S Capture/compare 2 selection 8 2 IC1F Input capture 1 filter 4 4 IC1PSC Input capture 1 prescaler 2 2 CC1S Capture/Compare 1 selection 0 2 CHCTLR2_Output CHCTLR2_Output capture/compare mode register 2 (output mode) 0x1C 0x20 read-write 0x0000 OC4CE Output compare 4 clear enable 15 1 OC4M Output compare 4 mode 12 3 OC4PE Output compare 4 preload enable 11 1 OC4FE Output compare 4 fast enable 10 1 CC4S Capture/Compare 4 selection 8 2 OC3CE Output compare 3 clear enable 7 1 OC3M Output compare 3 mode 4 3 OC3PE Output compare 3 preload enable 3 1 OC3FE Output compare 3 fast enable 2 1 CC3S Capture/Compare 3 selection 0 2 CHCTLR2_Input CHCTLR2_Input capture/compare mode register 2 (input mode) CHCTLR2_Output 0x1C 0x20 read-write 0x0000 IC4F Input capture 4 filter 12 4 IC4PSC Input capture 4 prescaler 10 2 CC4S Capture/Compare 4 selection 8 2 IC3F Input capture 3 filter 4 4 IC3PSC Input capture 3 prescaler 2 2 CC3S Capture/Compare 3 selection 0 2 CCER CCER capture/compare enable register 0x20 0x20 read-write 0x0000 CC4P Capture/Compare 3 output Polarity 13 1 CC4E Capture/Compare 4 output enable 12 1 CC3P Capture/Compare 3 output Polarity 9 1 CC3E Capture/Compare 3 output enable 8 1 CC2P Capture/Compare 2 output Polarity 5 1 CC2E Capture/Compare 2 output enable 4 1 CC1P Capture/Compare 1 output Polarity 1 1 CC1E Capture/Compare 1 output enable 0 1 CNT CNT counter 0x24 0x20 read-write 0x0000 CNT counter value 0 16 PSC PSC prescaler 0x28 0x20 read-write 0x0000 PSC Prescaler value 0 16 ATRLR ATRLR auto-reload register 0x2C 0x20 read-write 0x0000 ATRLR Auto-reload value 0 16 CH1CVR CH1CVR capture/compare register 1 0x34 0x20 read-write 0x0000 CH1CVR Capture/Compare 1 value 0 16 CH2CVR CH2CVR capture/compare register 2 0x38 0x20 read-write 0x0000 CH2CVR Capture/Compare 2 value 0 16 CH3CVR CH3CVR capture/compare register 3 0x3C 0x20 read-write 0x0000 CH3CVR Capture/Compare value 0 16 CH4CVR CH4CVR capture/compare register 4 0x40 0x20 read-write 0x0000 CH4CVR Capture/Compare value 0 16 DMACFGR DMACFGR DMA control register 0x48 0x20 read-write 0x0000 DBL DMA burst length 8 5 DBA DMA base address 0 5 DMAADR DMAADR DMA address for full transfer 0x4C 0x20 read-write 0x0000 DMAADR DMA register for burst accesses 0 16 I2C1 Inter integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C1 event interrupt 30 I2C1_ER I2C1 error interrupt 31 CTLR1 CTLR1 Control register 1 0x0 0x20 read-write 0x0000 SWRST Software reset 15 1 PEC Packet error checking 12 1 POS Acknowledge/PEC Position (for data reception) 11 1 ACK Acknowledge enable 10 1 STOP Stop generation 9 1 START Start generation 8 1 NOSTRETCH Clock stretching disable (Slave mode) 7 1 ENGC General call enable 6 1 ENPEC PEC enable 5 1 ENARP ARP enable 4 1 PE Peripheral enable 0 1 CTLR2 CTLR2 Control register 2 0x4 0x20 read-write 0x0000 LAST DMA last transfer 12 1 DMAEN DMA requests enable 11 1 ITBUFEN Buffer interrupt enable 10 1 ITEVTEN Event interrupt enable 9 1 ITERREN Error interrupt enable 8 1 FREQ Peripheral clock frequency 0 6 OADDR1 OADDR1 Own address register 1 0x8 0x20 read-write 0x0000 ADDMODE Addressing mode (slave mode) 15 1 ADD9_8 Interface address 8 2 ADD7_1 Interface address 1 7 ADD0 Interface address 0 1 OADDR2 OADDR2 Own address register 2 0xC 0x20 read-write 0x0000 ADD2 Interface address 1 7 ENDUAL Dual addressing mode enable 0 1 DATAR DATAR Data register 0x10 0x20 read-write 0x0000 DATAR 8-bit data register 0 8 STAR1 STAR1 Status register 1 0x14 0x20 0x0000 PECERR PEC Error in reception 12 1 read-write OVR Overrun/Underrun 11 1 read-write AF Acknowledge failure 10 1 read-write ARLO Arbitration lost (master mode) 9 1 read-write BERR Bus error 8 1 read-write TxE Data register empty (transmitters) 7 1 read-only RxNE Data register not empty (receivers) 6 1 read-only STOPF Stop detection (slave mode) 4 1 read-only ADD10 10-bit header sent (Master mode) 3 1 read-only BTF Byte transfer finished 2 1 read-only ADDR Address sent (master mode)/matched (slave mode) 1 1 read-only SB Start bit (Master mode) 0 1 read-only STAR2 STAR2 Status register 2 0x18 0x20 read-only 0x0000 PEC acket error checking register 8 8 DUALF Dual flag (Slave mode) 7 1 GENCALL General call address (Slave mode) 4 1 TRA Transmitter/receiver 2 1 BUSY Bus busy 1 1 MSL Master/slave 0 1 CKCFGR CKCFGR Clock control register 0x1C 0x20 read-write 0x0000 F_S I2C master mode selection 15 1 DUTY Fast mode duty cycle 14 1 CCR Clock control register in Fast/Standard mode (Master mode) 0 12 SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global interrupt 33 CTLR1 CTLR1 control register 1 0x0 0x20 read-write 0x0000 BIDIMODE Bidirectional data mode enable 15 1 BIDIOE Output enable in bidirectional mode 14 1 CRCEN Hardware CRC calculation enable 13 1 CRCNEXT CRC transfer next 12 1 DFF Data frame format 11 1 RXONLY Receive only 10 1 SSM Software slave management 9 1 SSI Internal slave select 8 1 LSBFIRST Frame format 7 1 SPE SPI enable 6 1 BR Baud rate control 3 3 MSTR Master selection 2 1 CPOL Clock polarity 1 1 CPHA Clock phase 0 1 CTLR2 CTLR2 control register 2 0x4 0x20 read-write 0x0000 TXEIE Tx buffer empty interrupt enable 7 1 RXNEIE RX buffer not empty interrupt enable 6 1 ERRIE Error interrupt enable 5 1 SSOE SS output enable 2 1 TXDMAEN Tx buffer DMA enable 1 1 RXDMAEN Rx buffer DMA enable 0 1 STATR STATR status register 0x8 0x20 0x0002 BSY Busy flag 7 1 read-only OVR Overrun flag 6 1 read-write MODF Mode fault 5 1 read-only CRCERR CRC error flag 4 1 read-write CHSID Channel side 2 1 read-only UDR Underrun flag 3 1 read-only TXE Transmit buffer empty 1 1 read-only RXNE Receive buffer not empty 0 1 read-only DATAR DATAR data register 0xC 0x20 read-write 0x0000 DATAR Data register 0 16 CRCR CRCR CRCR polynomial register 0x10 0x20 read-write 0x0007 CRCPOLY CRC polynomial register 0 16 RCRCR RCRCR RX CRC register 0x14 0x20 read-only 0x0000 RXCRC Rx CRC register 0 16 TCRCR TCRCR send CRC register 0x18 0x20 read-only 0x0000 TXCRC Tx CRC register 0 16 HSCR HSCR high speed control register 0x24 0x20 0x0000 HSRXEN High speed mode read enable 0 1 write-only USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global interrupt 32 STATR STATR Status register 0x0 0x20 0x000000C0 CTS CTS flag 9 1 read-write LBD LIN break detection flag 8 1 read-write TXE Transmit data register empty 7 1 read-only TC Transmission complete 6 1 read-write RXNE Read data register not empty 5 1 read-write IDLE IDLE line detected 4 1 read-only ORE Overrun error 3 1 read-only NE Noise error flag 2 1 read-only FE Framing error 1 1 read-only PE Parity error 0 1 read-only DATAR DATAR Data register 0x4 0x20 read-write 0x00000000 DR Data value 0 9 BRR BRR Baud rate register 0x8 0x20 read-write 0x00000000 DIV_Mantissa mantissa of USARTDIV 4 12 DIV_Fraction fraction of USARTDIV 0 4 CTLR1 CTLR1 Control register 1 0xC 0x20 read-write 0x00000000 UE USART enable 13 1 M Word length 12 1 WAKE Wakeup method 11 1 PCE Parity control enable 10 1 PS Parity selection 9 1 PEIE PE interrupt enable 8 1 TXEIE TXE interrupt enable 7 1 TCIE Transmission complete interrupt enable 6 1 RXNEIE RXNE interrupt enable 5 1 IDLEIE IDLE interrupt enable 4 1 TE Transmitter enable 3 1 RE Receiver enable 2 1 RWU Receiver wakeup 1 1 SBK Send break 0 1 CTLR2 CTLR2 Control register 2 0x10 0x20 read-write 0x00000000 LINEN LIN mode enable 14 1 STOP STOP bits 12 2 CLKEN Clock enable 11 1 CPOL Clock polarity 10 1 CPHA Clock phase 9 1 LBCL Last bit clock pulse 8 1 LBDIE LIN break detection interrupt enable 6 1 LBDL lin break detection length 5 1 ADD Address of the USART node 0 4 CTLR3 CTLR3 Control register 3 0x14 0x20 read-write 0x00000000 CTSIE CTS interrupt enable 10 1 CTSE CTS enable 9 1 RTSE RTS enable 8 1 DMAT DMA enable transmitter 7 1 DMAR DMA enable receiver 6 1 SCEN Smartcard mode enable 5 1 NACK Smartcard NACK enable 4 1 HDSEL Half-duplex selection 3 1 IRLP IrDA low-power 2 1 IREN IrDA mode enable 1 1 EIE Error interrupt enable 0 1 GPR GPR Guard time and prescaler register 0x18 0x20 read-write 0x00000000 GT Guard time value 8 8 PSC Prescaler value 0 8 ADC1 Analog to digital converter ADC1 0x40012400 0x0 0x400 registers ADC ADC global interrupt 29 STATR STATR status register 0x0 0x20 read-write 0x00000000 STRT Regular channel start flag 4 1 JSTRT Injected channel start flag 3 1 JEOC Injected channel end of conversion 2 1 EOC Regular channel end of conversion 1 1 AWD Analog watchdog flag 0 1 CTLR1 CTLR1 control register 1/TKEY_V_CTLR 0x4 0x20 read-write 0x00000000 ADC_CAL_VOL ADC Calibration voltage selection 25 2 AWDEN Analog watchdog enable on regular channels 23 1 JAWDEN Analog watchdog enable on injected channels 22 1 DISCNUM Discontinuous mode channel count 13 3 JDISCEN Discontinuous mode on injected channels 12 1 DISCEN Discontinuous mode on regular channels 11 1 JAUTO Automatic injected group conversion 10 1 AWDSGL Enable the watchdog on a single channel in scan mode 9 1 SCAN Scan mode enable 8 1 JEOCIE Interrupt enable for injected channels 7 1 AWDIE Analog watchdog interrupt enable 6 1 EOCIE Interrupt enable for EOC 5 1 AWDCH Analog watchdog channel select bits 0 5 CTLR2 CTLR2 control register 2 0x8 0x20 read-write 0x00000000 SWSTART Start conversion of regular channels 22 1 JSWSTART Start conversion of injected channels 21 1 EXTTRIG External trigger conversion mode for regular channels 20 1 EXTSEL External event select for regular group 17 3 JEXTTRIG External trigger conversion mode for injected channels 15 1 JEXTSEL External event select for injected group 12 3 ALIGN Data alignment 11 1 DMA Direct memory access mode 8 1 RSTCAL Reset calibration 3 1 CAL A/D calibration 2 1 CONT Continuous conversion 1 1 ADON A/D converter ON / OFF 0 1 SAMPTR1_CHARGE1 SAMPTR1_CHARGE1 sample time register 1 0xC 0x20 read-write 0x00000000 SMP10_TKCG10 Channel 10 sample time selection 0 3 SMP11_TKCG11 Channel 11 sample time selection 3 3 SMP12_TKCG12 Channel 12 sample time selection 6 3 SMP13_TKCG13 Channel 13 sample time selection 9 3 SMP14_TKCG14 Channel 14 sample time selection 12 3 SMP15_TKCG15 Channel 15 sample time selection 15 3 SAMPTR2_CHARGE2 SAMPTR2_CHARGE2 sample time register 2 0x10 0x20 read-write 0x00000000 SMP0_TKCG0 Channel 0 sample time selection 0 3 SMP1_TKCG1 Channel 1 sample time selection 3 3 SMP2_TKCG2 Channel 2 sample time selection 6 3 SMP3_TKCG3 Channel 3 sample time selection 9 3 SMP4_TKCG4 Channel 4 sample time selection 12 3 SMP5_TKCG5 Channel 5 sample time selection 15 3 SMP6_TKCG6 Channel 6 sample time selection 18 3 SMP7_TKCG7 Channel 7 sample time selection 21 3 SMP8_TKCG8 Channel 8 sample time selection 24 3 SMP9_TKCG9 Channel 9 sample time selection 27 3 IOFR1 IOFR1 injected channel data offset register x 0x14 0x20 read-write 0x00000000 JOFFSET1 Data offset for injected channel x 0 10 IOFR2 IOFR2 injected channel data offset register x 0x18 0x20 read-write 0x00000000 JOFFSET2 Data offset for injected channel x 0 10 IOFR3 IOFR3 injected channel data offset register x 0x1C 0x20 read-write 0x00000000 JOFFSET3 Data offset for injected channel x 0 10 IOFR4 IOFR4 injected channel data offset register x 0x20 0x20 read-write 0x00000000 JOFFSET4 Data offset for injected channel x 0 10 WDHTR WDHTR watchdog higher threshold register 0x24 0x20 read-write 0x00000000 HT Analog watchdog higher threshold 0 10 WDLTR WDLTR watchdog lower threshold register 0x28 0x20 read-write 0x00000000 LT Analog watchdog lower threshold 0 10 RSQR1 RSQR1 regular sequence register 1 0x2C 0x20 read-write 0x00000000 L Regular channel sequence length 20 4 SQ16 16th conversion in regular sequence 15 5 SQ15 15th conversion in regular sequence 10 5 SQ14 14th conversion in regular sequence 5 5 SQ13 13th conversion in regular sequence 0 5 RSQR2 RSQR2 regular sequence register 2 0x30 0x20 read-write 0x00000000 SQ12 12th conversion in regular sequence 25 5 SQ11 11th conversion in regular sequence 20 5 SQ10 10th conversion in regular sequence 15 5 SQ9 9th conversion in regular sequence 10 5 SQ8 8th conversion in regular sequence 5 5 SQ7 7th conversion in regular sequence 0 5 RSQR3 RSQR3 regular sequence register 3 0x34 0x20 read-write 0x00000000 SQ6 6th conversion in regular sequence 25 5 SQ5 5th conversion in regular sequence 20 5 SQ4 4th conversion in regular sequence 15 5 SQ3 3rd conversion in regular sequence 10 5 SQ2 2nd conversion in regular sequence 5 5 SQ1 1st conversion in regular sequence 0 5 ISQR ISQR injected sequence register 0x38 0x20 read-write 0x00000000 JL Injected sequence length 20 2 JSQ4 4th conversion in injected sequence 15 5 JSQ3 3rd conversion in injected sequence 10 5 JSQ2 2nd conversion in injected sequence 5 5 JSQ1 1st conversion in injected sequence 0 5 IDATAR1 IDATAR1 injected data register 1 0x3C 0x20 read-only 0x00000000 IDATA Injected data 0 16 IDATAR2 IDATAR2 injected data register 2 0x40 0x20 read-only 0x00000000 IDATA Injected data 0 16 IDATAR3 IDATAR3 injected data register 3 0x44 0x20 read-only 0x00000000 IDATA Injected data 0 16 IDATAR4 IDATAR4 injected data register 4 0x48 0x20 read-only 0x00000000 IDATA Injected data 0 16 RDATAR RDATAR regular data register 0x4C 0x20 read-only 0x00000000 DATA Regular data 0 32 DLYR DLYR delay data register 0x50 0x20 read-write 0x00000000 DLYVLU External trigger data delay time configuration 0 9 DLYSRC External trigger source delay selection 9 1 DBG Debug support DBG 0xE000D000 0x0 0x400 registers CFGR1 CFGR1 DBGMCU_CFGR1 0x0 0x20 read-write 0x0 DEG_IWDG DEG_IWDG 0 1 DEG_WWDG DEG_WWDG 1 1 DEG_I2C1 DEG_I2C1 2 1 DEG_TIM1 DEG_TIM1 4 1 DEG_TIM2 DEG_TIM2 5 1 CFGR2 CFGR2 DBGMCU_CFGR2 0x4 0x20 read-write 0x0 DBG_SLEEP DBG_SLEEP 0 1 DBG_STOP DBG_STOP 1 1 DBG_STANDBY DBG_STANDBY 2 1 ESIG Device electronic signature ESIG 0x1FFFF7E0 0x0 0x14 registers FLACAP FLACAP Flash capacity register 0x0 0x10 read-only 0x0000 FLASHSIZE Flash size 0 16 UNIID1 UNIID1 Unique identity 1 0x8 0x20 read-only 0x00000000 U_ID Unique identity[31:0] 0 32 UNIID2 UNIID2 Unique identity 2 0xC 0x20 read-only 0x00000000 U_ID Unique identity[63:32] 0 32 UNIID3 UNIID3 Unique identity 3 0x10 0x20 read-only 0x00000000 U_ID Unique identity[95:64] 0 32 FLASH FLASH FLASH 0x40022000 0x0 0x400 registers FLASH Flash global interrupt 18 ACTLR ACTLR Flash key register 0x0 0x20 0x00000000 LATENCY Number of FLASH wait states 0 1 read-write KEYR KEYR Flash key register 0x4 0x20 write-only 0x00000000 KEYR FPEC key 0 32 OBKEYR OBKEYR Flash option key register 0x8 0x20 write-only 0x00000000 OPTKEY Option byte key 0 32 STATR STATR Status register 0xC 0x20 0x00008000 BOOT_LOCK BOOT lock 15 1 read-write BOOT_MODE BOOT mode 14 1 read-write EOP End of operation 5 1 read-write WRPRTERR Write protection error 4 1 read-write BSY Busy 0 1 read-only CTLR CTLR Control register 0x10 0x20 read-write 0x00008080 PG Programming 0 1 PER Page Erase 1 1 MER Mass Erase 2 1 OBPG Option byte programming 4 1 OBER Option byte erase 5 1 STRT Start 6 1 LOCK Lock 7 1 OBWRE Option bytes write enable 9 1 ERRIE Error interrupt enable 10 1 EOPIE End of operation interrupt enable 12 1 FLOCK Fast programmable lock 15 1 PAGE_PG Fast programming 16 1 PAGE_ER Fast erase 17 1 BUFLOAD Buffer load 18 1 BUFRST Buffer reset 19 1 ADDR ADDR Flash address register 0x14 0x20 write-only 0x00000000 ADDR Flash Address 0 32 OBR OBR Option byte register 0x1C 0x20 read-only 0x03FFFFFE OBERR Option byte error 0 1 RDPRT Read protection 1 1 IWDG_SW IWDG_SW 2 1 STOP_RST STOP_RST 3 1 STANDY_RST STANDY_RST 4 1 CFG_RST_MODE CFG_RST_MODE 5 2 DATA0 DATA0 10 8 DATA1 DATA1 18 8 WPR WPR Write protection register 0x20 0x20 read-only 0xFFFFFFFF WRP Write protect 0 32 MODEKEYR MODEKEYR Mode select register 0x24 0x20 write-only 0x00000000 MODEKEYR Mode select 0 32 BOOT_MODEKEYP BOOT_MODEKEYP Boot mode key register 0x28 0x20 write-only 0x00000000 MODEKEYR Boot mode key 0 32 PFIC Programmable Fast Interrupt Controller PFIC 0xE000E000 0x00 0x1100 registers ISR1 ISR1 Interrupt Status Register 0x00 0x20 read-only 0x0000000C INTENSTA2_3 Interrupt ID Status 2 2 INTENSTA12_31 Interrupt ID Status 12 20 ISR2 ISR2 Interrupt Status Register 0x04 0x20 read-only 0x00000000 INTENSTA Interrupt ID Status 0 32 ISR3 ISR3 Interrupt Status Register 0x08 0x20 read-only 0x00000000 INTENSTA Interrupt ID Status 0 32 ISR4 ISR4 Interrupt Status Register 0x0C 0x20 read-only 0x00000000 INTENSTA Interrupt ID Status 0 8 IPR1 IPR1 Interrupt Pending Register 0x20 0x20 read-only 0x00000000 PENDSTA2_3 PENDSTA 2 2 PENDSTA12_31 PENDSTA 12 20 IPR2 IPR2 Interrupt Pending Register 0x24 0x20 read-only 0x00000000 PENDSTA PENDSTA 0 32 IPR3 IPR3 Interrupt Pending Register 0x28 0x20 read-only 0x00000000 PENDSTA PENDSTA 0 32 IPR4 IPR4 Interrupt Pending Register 0x2C 0x20 read-only 0x00000000 PENDSTA PENDSTA 0 8 ITHRESDR ITHRESDR Interrupt Priority Register 0x40 0x20 read-write 0x00000000 THRESHOLD THRESHOLD 0 8 CFGR CFGR Interrupt Config Register 0x48 0x20 0x00000000 RESETSYS RESETSYS write-only 7 1 KEYCODE KEYCODE write-only 16 16 GISR GISR Interrupt Global Register 0x4C 0x20 read-only 0x00000000 NESTSTA NESTSTA 0 8 GACTSTA GACTSTA 8 1 GPENDSTA GPENDSTA 9 1 VTFIDR VTFIDR ID Config Register 0x50 0x20 read-write 0x00000000 VTFID0 VTFID0 0 8 VTFID1 VTFID1 8 8 VTFID2 VTFID2 16 8 VTFID3 VTFID3 24 8 VTFADDRR0 VTFADDRR0 Interrupt 0 address Register 0x60 0x20 read-write 0x00000000 VTF0EN VTF0EN 0 1 ADDR0 ADDR0 1 31 VTFADDRR1 VTFADDRR1 Interrupt 1 address Register 0x64 0x20 read-write 0x00000000 VTF1EN VTF1EN 0 1 ADDR1 ADDR1 1 31 VTFADDRR2 VTFADDRR2 Interrupt 2 address Register 0x68 0x20 read-write 0x00000000 VTF2EN VTF2EN 0 1 ADDR2 ADDR2 1 31 VTFADDRR3 VTFADDRR3 Interrupt 3 address Register 0x6C 0x20 read-write 0x00000000 VTF3EN VTF3EN 0 1 ADDR3 ADDR3 1 31 IENR1 IENR1 Interrupt Setting Register 0x100 0x20 write-only 0x00000000 INTEN INTEN 12 20 IENR2 IENR2 Interrupt Setting Register 0x104 0x20 write-only 0x00000000 INTEN INTEN 0 32 IENR3 IENR3 Interrupt Setting Register 0x108 0x20 write-only 0x00000000 INTEN INTEN 0 32 IENR4 IENR4 Interrupt Setting Register 0x10C 0x20 write-only 0x00000000 INTEN INTEN 0 8 IRER1 IRER1 Interrupt Clear Register 0x180 0x20 write-only 0x00000000 INTRSET INTRSET 12 20 IRER2 IRER2 Interrupt Clear Register 0x184 0x20 write-only 0x00000000 INTRSET INTRSET 0 32 IRER3 IRER3 Interrupt Clear Register 0x188 0x20 write-only 0x00000000 INTRSET INTRSET 0 32 IRER4 IRER4 Interrupt Clear Register 0x18C 0x20 write-only 0x00000000 INTRSET INTRSET 0 8 IPSR1 IPSR1 Interrupt Pending Register 0x200 0x20 write-only 0x00000000 PENDSET2_3 PENDSET 2 2 PENDSET12_31 PENDSET 12 20 IPSR2 IPSR2 Interrupt Pending Register 0x204 0x20 write-only 0x00000000 PENDSET PENDSET 0 32 IPSR3 IPSR3 Interrupt Pending Register 0x208 0x20 write-only 0x00000000 PENDSET PENDSET 0 32 IPSR4 IPSR4 Interrupt Pending Register 0x20C 0x20 write-only 0x00000000 PENDSET PENDSET 0 8 IPRR1 IPRR1 Interrupt Pending Clear Register 0x280 0x20 write-only 0x00000000 PENDRESET2_3 PENDRESET 2 2 PENDRESET12_31 PENDRESET 12 20 IPRR2 IPRR2 Interrupt Pending Clear Register 0x284 0x20 write-only 0x00000000 PENDRESET PENDRESET 0 32 IPRR3 IPRR3 Interrupt Pending Clear Register 0x288 0x20 write-only 0x00000000 PENDRESET PENDRESET 0 32 IPRR4 IPRR4 Interrupt Pending Clear Register 0x28C 0x20 write-only 0x00000000 PENDRESET PENDRESET 0 8 IACTR1 IACTR1 Interrupt ACTIVE Register 0x300 0x20 write-only 0x00000000 IACTS2_3 IACTS 2 2 IACTS12_31 IACTS 12 20 IACTR2 IACTR2 Interrupt ACTIVE Register 0x304 0x20 write-only 0x00000000 IACTS IACTS 0 32 IACTR3 IACTR3 Interrupt ACTIVE Register 0x308 0x20 write-only 0x00000000 IACTS IACTS 0 32 IACTR4 IACTR4 Interrupt ACTIVE Register 0x30C 0x20 write-only 0x00000000 IACTS IACTS 0 8 IPRIOR0 IPRIOR0 Interrupt Priority Register 0x400 0x8 read-write 0x00000000 IPRIOR1 IPRIOR1 Interrupt Priority Register 0x401 0x8 read-write 0x00000000 IPRIOR2 IPRIOR2 Interrupt Priority Register 0x402 0x8 read-write 0x00000000 IPRIOR3 IPRIOR3 Interrupt Priority Register 0x403 0x8 read-write 0x00000000 IPRIOR4 IPRIOR4 Interrupt Priority Register 0x404 0x8 read-write 0x00000000 IPRIOR5 IPRIOR5 Interrupt Priority Register 0x405 0x8 read-write 0x00000000 IPRIOR6 IPRIOR6 Interrupt Priority Register 0x406 0x8 read-write 0x00000000 IPRIOR7 IPRIOR7 Interrupt Priority Register 0x407 0x8 read-write 0x00000000 IPRIOR8 IPRIOR8 Interrupt Priority Register 0x408 0x8 read-write 0x00000000 IPRIOR9 IPRIOR9 Interrupt Priority Register 0x409 0x8 read-write 0x00000000 IPRIOR10 IPRIOR10 Interrupt Priority Register 0x40A 0x8 read-write 0x00000000 IPRIOR11 IPRIOR11 Interrupt Priority Register 0x40B 0x8 read-write 0x00000000 IPRIOR12 IPRIOR12 Interrupt Priority Register 0x40C 0x8 read-write 0x00000000 IPRIOR13 IPRIOR13 Interrupt Priority Register 0x40D 0x8 read-write 0x00000000 IPRIOR14 IPRIOR14 Interrupt Priority Register 0x40E 0x8 read-write 0x00000000 IPRIOR15 IPRIOR15 Interrupt Priority Register 0x40F 0x8 read-write 0x00000000 IPRIOR16 IPRIOR6 Interrupt Priority Register 0x410 0x8 read-write 0x00000000 IPRIOR17 IPRIOR7 Interrupt Priority Register 0x411 0x8 read-write 0x00000000 IPRIOR18 IPRIOR8 Interrupt Priority Register 0x412 0x8 read-write 0x00000000 IPRIOR19 IPRIOR9 Interrupt Priority Register 0x413 0x8 read-write 0x00000000 IPRIOR20 IPRIOR20 Interrupt Priority Register 0x414 0x8 read-write 0x00000000 IPRIOR21 IPRIOR21 Interrupt Priority Register 0x415 0x8 read-write 0x00000000 IPRIOR22 IPRIOR22 Interrupt Priority Register 0x416 0x8 read-write 0x00000000 IPRIOR23 IPRIOR23 Interrupt Priority Register 0x417 0x8 read-write 0x00000000 IPRIOR24 IPRIOR24 Interrupt Priority Register 0x418 0x8 read-write 0x00000000 IPRIOR25 IPRIOR25 Interrupt Priority Register 0x419 0x8 read-write 0x00000000 IPRIOR26 IPRIOR26 Interrupt Priority Register 0x41A 0x8 read-write 0x00000000 IPRIOR27 IPRIOR27 Interrupt Priority Register 0x41B 0x8 read-write 0x00000000 IPRIOR28 IPRIOR28 Interrupt Priority Register 0x41C 0x8 read-write 0x00000000 IPRIOR29 IPRIOR29 Interrupt Priority Register 0x41D 0x8 read-write 0x00000000 IPRIOR30 IPRIOR30 Interrupt Priority Register 0x41E 0x8 read-write 0x00000000 IPRIOR31 IPRIOR31 Interrupt Priority Register 0x41F 0x8 read-write 0x00000000 IPRIOR32 IPRIOR32 Interrupt Priority Register 0x420 0x8 read-write 0x00000000 IPRIOR33 IPRIOR33 Interrupt Priority Register 0x421 0x8 read-write 0x00000000 IPRIOR34 IPRIOR34 Interrupt Priority Register 0x422 0x8 read-write 0x00000000 IPRIOR35 IPRIOR35 Interrupt Priority Register 0x423 0x8 read-write 0x00000000 IPRIOR36 IPRIOR36 Interrupt Priority Register 0x424 0x8 read-write 0x00000000 IPRIOR37 IPRIOR37 Interrupt Priority Register 0x425 0x8 read-write 0x00000000 IPRIOR38 IPRIOR38 Interrupt Priority Register 0x426 0x8 read-write 0x00000000 IPRIOR39 IPRIOR39 Interrupt Priority Register 0x427 0x8 read-write 0x00000000 IPRIOR40 IPRIOR40 Interrupt Priority Register 0x428 0x8 read-write 0x00000000 IPRIOR41 IPRIOR41 Interrupt Priority Register 0x429 0x8 read-write 0x00000000 IPRIOR42 IPRIOR42 Interrupt Priority Register 0x42A 0x8 read-write 0x00000000 IPRIOR43 IPRIOR43 Interrupt Priority Register 0x42B 0x8 read-write 0x00000000 IPRIOR44 IPRIOR44 Interrupt Priority Register 0x42C 0x8 read-write 0x00000000 IPRIOR45 IPRIOR45 Interrupt Priority Register 0x42D 0x8 read-write 0x00000000 IPRIOR46 IPRIOR46 Interrupt Priority Register 0x42E 0x8 read-write 0x00000000 IPRIOR47 IPRIOR47 Interrupt Priority Register 0x42F 0x8 read-write 0x00000000 IPRIOR48 IPRIOR48 Interrupt Priority Register 0x430 0x8 read-write 0x00000000 IPRIOR49 IPRIOR49 Interrupt Priority Register 0x431 0x8 read-write 0x00000000 IPRIOR50 IPRIOR50 Interrupt Priority Register 0x432 0x8 read-write 0x00000000 IPRIOR51 IPRIOR51 Interrupt Priority Register 0x433 0x8 read-write 0x00000000 IPRIOR52 IPRIOR52 Interrupt Priority Register 0x434 0x8 read-write 0x00000000 IPRIOR53 IPRIOR53 Interrupt Priority Register 0x435 0x8 read-write 0x00000000 IPRIOR54 IPRIOR54 Interrupt Priority Register 0x436 0x8 read-write 0x00000000 IPRIOR55 IPRIOR55 Interrupt Priority Register 0x437 0x8 read-write 0x00000000 IPRIOR56 IPRIOR56 Interrupt Priority Register 0x438 0x8 read-write 0x00000000 IPRIOR57 IPRIOR57 Interrupt Priority Register 0x439 0x8 read-write 0x00000000 IPRIOR58 IPRIOR58 Interrupt Priority Register 0x43A 0x8 read-write 0x00000000 IPRIOR59 IPRIOR59 Interrupt Priority Register 0x43B 0x8 read-write 0x00000000 IPRIOR60 IPRIOR60 Interrupt Priority Register 0x43C 0x8 read-write 0x00000000 IPRIOR61 IPRIOR61 Interrupt Priority Register 0x43D 0x8 read-write 0x00000000 IPRIOR62 IPRIOR62 Interrupt Priority Register 0x43E 0x8 read-write 0x00000000 IPRIOR63 IPRIOR63 Interrupt Priority Register 0x43F 0x8 read-write 0x00000000 SCTLR SCTLR System Control Register 0xd10 0x20 read-write 0x00000000 SLEEPONEXIT SLEEPONEXIT 1 1 SLEEPDEEP SLEEPDEEP 2 1 WFITOWFE WFITOWFE 3 1 SEVONPEND SEVONPEND 4 1 SETEVENT SETEVENT 5 1 SYSRESET SYSRESET 31 1 STK_CTLR STK_CTLR System counter control register 0x1000 0x20 0x00000000 STE System counter enable read-write 0 1 STIE System counter interrupt enable read-write 1 1 STCLK System selects the clock source read-write 2 1 STRE System reload register read-write 3 1 MODE System Mode read-write 4 1 INIT System Initialization update read-write 5 1 SWIE System software triggered interrupts enable read-write 31 1 STK_SR System START 0x1004 0x20 read-write 0x00000000 CNTIF CNTIF 0 1 STK_CNTL System counter low register 0x1008 0x20 read-write 0x00000000 CNTL CNTL 0 32 STK_CMPLR System compare low register 0x1010 0x20 read-write 0x00000000 CMPL CMPL 0 32