diff --git a/pwm/pwmclass.cpp b/pwm/pwmclass.cpp
index 3561e2f..0371556 100644
--- a/pwm/pwmclass.cpp
+++ b/pwm/pwmclass.cpp
@@ -69,7 +69,7 @@ static inline void tim1pwm_init () noexcept {
   TIM1.CTLR1.B.CEN     = SET;
 }
 typedef __SIZE_TYPE__ size_t;
-static void dma1ch5_init (void * ptr) {
+static inline void dma1ch5_init (void * ptr) noexcept {
 	// Enable DMA
   RCC.AHBPCENR.modify([](RCC_Type::AHBPCENR_DEF & r) -> auto {
     r.B.SRAMEN = SET;
@@ -78,9 +78,10 @@ static void dma1ch5_init (void * ptr) {
   });
 	// DMA5 can be configured to attach to T1UP
 	// The system can only DMA out at ~2.2MSPS.  2MHz is stable.
-  DMA1.CNTR5.R  = FULL_LEN;
+  DMA1.CNTR5 .R = FULL_LEN;
   DMA1.MADDR5.R = reinterpret_cast<size_t>(ptr);
   DMA1.PADDR5.R = reinterpret_cast<size_t>(& TIM1.CH1CVR);
+  NVIC.EnableIRQ (DMA1_Channel5_IRQn);
   DMA1.CFGR5.modify([](DMA1_Type::CFGR5_DEF & r) -> auto {
     r.B.DIR   = SET;                    // MEM2PERIPHERAL
     r.B.PL    = 2u;                     // High priority.
@@ -90,10 +91,10 @@ static void dma1ch5_init (void * ptr) {
     r.B.CIRC  = SET;                    // Circular mode.
     r.B.HTIE  = SET;                    // Half-trigger
     r.B.TCIE  = SET;                    // Whole-trigger
+    // Enable DMA1 ch5
+    r.B.EN    = SET;
     return r.R;
   });
-  NVIC.EnableIRQ (DMA1_Channel5_IRQn);
-  DMA1.CFGR5.B.EN = SET;
 }
 
 PwmClass::PwmClass() noexcept : pL(buffer), pH(buffer + HALF_LEN), src(nullptr) {