108 lines
3.3 KiB
C++
108 lines
3.3 KiB
C++
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#include "pwmclass.h"
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#include "gpio.h"
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typedef __SIZE_TYPE__ size_t;
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extern "C" {
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[[gnu::interrupt]] extern void DMA1_Channel2_IRQHandler( void );
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};
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static PwmClass * pPwmInstance = nullptr;
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void DMA1_Channel2_IRQHandler( void ) {
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DMA1_Type::INTFR_DEF state (DMA1.INTFR);
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if (state.B.GIF2 != RESET) {
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DMA1.INTFCR.B.CGIF2 = SET;
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} else return;
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if (state.B.HTIF2 != RESET) {
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DMA1.INTFCR.B.CHTIF2 = SET;
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if (pPwmInstance) pPwmInstance->send(false);
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}
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if (state.B.TCIF2 != RESET) {
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DMA1.INTFCR.B.CTCIF2 = SET;
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if (pPwmInstance) pPwmInstance->send(true);
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}
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}
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/*
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* initialize TIM2 for PWM
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*/
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inline void PwmClass::TimInit() noexcept {
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// Enable GPIOA and TIM1
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RCC.APB2PCENR.modify([] (RCC_Type::APB2PCENR_DEF & r) -> auto {
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r.B.IOPAEN = SET;
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r.B.IOPBEN = SET;
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//r.B.AFIOEN = SET;
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return r.R;
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});
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RCC.APB1PCENR.B.TIM2EN = SET;
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// PA2 is TIM2_CH3, 10MHz Output alt func, push-pull
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GPIOA.CFGLR.modify([](GPIOA_Type::CFGLR_DEF & r) -> auto {
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r.B.CNF2 = 2u;
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r.B.MODE2 = 1u;
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return r.R;
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});
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// PB1 is DEN, active H Output 10 MHz, push-pull
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GPIOB.CFGLR.modify([](GPIOA_Type::CFGLR_DEF & r) -> auto {
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r.B.CNF1 = 0u;
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r.B.MODE1 = 1u;
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return r.R;
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});
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GPIOB.BSHR.B.BS1 = SET; // set to H
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// Reset TIM2 to init all regs
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RCC.APB1PRSTR.B.TIM2RST = SET;
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RCC.APB1PRSTR.B.TIM2RST = RESET;
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// CTLR1: default is up, events generated, edge align
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// SMCFGR: default clk input is CK_INT
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// Prescaler
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TIM2.PSC.R = 0u; // 144 MHz
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// Auto Reload - sets period
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TIM2.ATRLR.R = MAXPWM - 1; // 24 kHz
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// CH3 Mode is output, PWM1 (CC3S = 00, OC3M = 110)
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TIM2.CHCTLR2_Output.modify([](TIM2_Type::CHCTLR2_Output_DEF & r) -> auto {
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r.B.OC3M = 0x6u;
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return r.R;
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});
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// Enable TIM1 outputs
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TIM2.CCER.modify([](TIM2_Type::CCER_DEF & r) -> auto {
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// Enable CH3, CH3 output, positive pol
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r.B.CC3E = SET;
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//r.B.CC3P = SET; // negative
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return r.R;
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});
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// Reload immediately + Trigger DMA
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TIM2.SWEVGR.B.UG = SET;
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TIM2.DMAINTENR.B.UDE = SET;
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}
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inline void PwmClass::DmaInit() noexcept {
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// Enable DMA
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RCC.AHBPCENR.modify([](RCC_Type::AHBPCENR_DEF & r) -> auto {
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r.B.SRAMEN = SET;
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r.B.DMA1EN = SET;
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return r.R;
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});
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// DMA can be configured to attach to T2UP
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// The system can only DMA out at ~2.2MSPS. 2MHz is stable.
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DMA1.CNTR2 .R = FULL_LEN;
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DMA1.MADDR2.R = reinterpret_cast<size_t>(buffer);
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DMA1.PADDR2.R = reinterpret_cast<size_t>(& TIM2.CH3CVR);
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NVIC.EnableIRQ (DMA1_Channel2_IRQn);
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DMA1.CFGR2.modify([](DMA1_Type::CFGR2_DEF & r) -> auto {
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r.B.DIR = SET; // MEM2PERIPHERAL
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r.B.PL = 2u; // High priority.
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r.B.PSIZE = 1u; // 16-bit peripheral
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r.B.MSIZE = 1u; // 16-bit memory
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r.B.MINC = SET; // Increase memory.
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r.B.CIRC = SET; // Circular mode.
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r.B.HTIE = SET; // Half-trigger
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r.B.TCIE = SET; // Whole-trigger
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// Enable DMA1 CH2
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r.B.EN = SET;
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return r.R;
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});
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}
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PwmClass::PwmClass() noexcept : count(0u), pL(buffer), pH(buffer + HALF_LEN), src(nullptr) {
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pPwmInstance = this;
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TimInit ();
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DmaInit ();
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// Enable TIM2
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TIM2.CTLR1.B.CEN = SET;
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}
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