105 lines
3.1 KiB
C++
105 lines
3.1 KiB
C++
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#include "system.h"
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#include "pwmclass.h"
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#include "gpio.h"
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static PwmClass * pInstance = nullptr;
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extern "C" void DMA1_Channel5_IRQHandler( void ) __attribute__((interrupt));
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void DMA1_Channel5_IRQHandler( void ) {
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DMA1_Type::INTFR_DEF state (DMA1.INTFR);
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DMA1.INTFCR.R = state.R; // clear all
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if (!pInstance) return;
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if (state.B.HTIF5 != RESET) pInstance->send(false);
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else if (state.B.TCIF5 != RESET) pInstance->send(true);
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}
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/*
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* initialize TIM1 for PWM
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*/
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static inline void tim1pwm_init () noexcept {
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// Enable GPIOD and TIM1
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RCC.APB2PCENR.modify([] (RCC_Type::APB2PCENR_DEF & r) -> auto {
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r.B.IOPDEN = SET;
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r.B.TIM1EN = SET;
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return r.R;
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});
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// PD0 is T1CH1N, PD2 is T1CH1, 10MHz Output alt func, push-pull
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GPIOD.CFGLR.modify([](GPIOA_Type::CFGLR_DEF & r) -> auto {
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r.B.CNF0 = 2u;
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r.B.MODE0 = 1u;
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r.B.CNF2 = 2u;
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r.B.MODE2 = 1u;
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return r.R;
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});
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// Reset TIM1 to init all regs
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RCC.APB2PRSTR.B.TIM1RST = SET;
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RCC.APB2PRSTR.B.TIM1RST = RESET;
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// CTLR1: default is up, events generated, edge align
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// SMCFGR: default clk input is CK_INT
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// Prescaler
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TIM1.PSC.R = 0u;
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// Auto Reload - sets period
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TIM1.ATRLR.R = MAXPWM - 1;
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TIM1.CCER.modify([](TIM1_Type::CCER_DEF & r) -> auto {
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// Enable CH1N, CH1 output, positive pol
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r.B.CC1NE = SET;
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r.B.CC1E = SET;
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/*
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r.B.CC1NP = SET; // active Low
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r.B.CC1P = SET;
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*/
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return r.R;
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});
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// CH1 Mode is output, PWM1 (CC1S = 00, OC1M = 110)
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TIM1.CHCTLR1_Output.modify([](TIM1_Type::CHCTLR1_Output_DEF & r) -> auto {
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r.B.OC1M = 0x6u;
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return r.R;
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});
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// Enable TIM1 outputs
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TIM1.BDTR.modify([](TIM1_Type::BDTR_DEF & r) -> auto {
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r.B.MOE = SET;
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//r.B.DTG = 48u; // Dead time 1us
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return r.R;
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});
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// Reload immediately + Trigger DMA
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TIM1.SWEVGR.B.UG = SET;
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TIM1.DMAINTENR.B.UDE = SET;
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// Enable TIM1
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TIM1.CTLR1.B.CEN = SET;
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}
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typedef __SIZE_TYPE__ size_t;
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static inline void dma1ch5_init (void * ptr) noexcept {
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// Enable DMA
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RCC.AHBPCENR.modify([](RCC_Type::AHBPCENR_DEF & r) -> auto {
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r.B.SRAMEN = SET;
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r.B.DMA1EN = SET;
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return r.R;
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});
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// DMA5 can be configured to attach to T1UP
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// The system can only DMA out at ~2.2MSPS. 2MHz is stable.
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DMA1.CNTR5 .R = FULL_LEN;
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DMA1.MADDR5.R = reinterpret_cast<size_t>(ptr);
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DMA1.PADDR5.R = reinterpret_cast<size_t>(& TIM1.CH1CVR);
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NVIC.EnableIRQ (DMA1_Channel5_IRQn);
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DMA1.CFGR5.modify([](DMA1_Type::CFGR5_DEF & r) -> auto {
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r.B.DIR = SET; // MEM2PERIPHERAL
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r.B.PL = 2u; // High priority.
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r.B.PSIZE = 1u; // 16-bit peripheral
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r.B.MSIZE = 1u; // 16-bit memory
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r.B.MINC = SET; // Increase memory.
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r.B.CIRC = SET; // Circular mode.
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r.B.HTIE = SET; // Half-trigger
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r.B.TCIE = SET; // Whole-trigger
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// Enable DMA1 ch5
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r.B.EN = SET;
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return r.R;
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});
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}
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PwmClass::PwmClass() noexcept : pL(buffer), pH(buffer + HALF_LEN), src(nullptr) {
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pInstance = this;
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tim1pwm_init ();
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dma1ch5_init (buffer);
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}
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